Texas Instruments SN74ACT7811-15FN, SN74ACT7811-15PN, SN74ACT7811-18FN, SN74ACT7811-18FNR, SN74ACT7811-18PN Datasheet
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SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Independent Asynchronous Inputs and
Outputs
D
1024 Words × 18 Bits
D
Read and Write Operations Can Be
Synchronized to Independent System
Clocks
D
Programmable Almost-Full/Almost-Empty
Flag
D
Pin-to-Pin Compatible With SN74ACT7881,
SN74ACT7882, and SN74ACT7884
D
Input-Ready, Output-Ready, and Half-Full
Flags
D
Cascadable in Word Width and/or Word
Depth
D
Fast Access Times of 15 ns With a 50-pF
Load
D
High-Output Drive for Direct Bus Interface
D
Available in 68-Pin PLCC (FN) and
Space-Saving 80-Pin Thin Quad Flat (PN)
Packages
28 29
V
CC
Q14
Q13
GND
Q12
Q11
V
CC
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
D14
D13
D12
D11
D10
D9
V
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
31 32 33 34
V
GND
87 65493
D17
GND
RDCLK
RDEN1
RDEN2OERESET
HF
V
Q0
Q1
WRTCLK
WRTEN1
WRTEN2
AF/AE
GND
IR
168672
35 36 37 38 39
66 65
27
DAF
GND
OR
V
64 63 62 61
40 41 42 43
GND
Q2
Q3
V
Q17
Q16
GND
Q15
D15
D16
CC
CC
CC
CC
V
CC
FN PACKAGE
(TOP VIEW)
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25
60
59
58
57
56
55
54
53
52
51
50
48
49
47
46
45
44
43
42
41
4026 27 28 29 30 31 32 33 34 35 36 37 38 39
80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 6172
NC
GND
GND
NC
NC
NC
NC
V
CC
NC
GND
Q16
Q17
OR
GND
V
CC
OE
RDEN2
RDEN1
RDCLK
D14
D16
D15
GND
D17
RESET
V
CC
GND
NC
D13
D12
D11
D10
D9
D8
D7D6D5D4D3D2D1
D0
DAF
V
CC
V
CC
GND
V
CC
GND
GND
V
CC
WRTCLK
WRTEN1
WRTEN2
AF/AE
IR
HF
Q1
Q0
Q2
Q3
Q4
Q5
GND
GND
Q6
Q7
V
CC
Q8
GND
Q9
Q10
Q11
V
CC
Q12
Q13
GND
GND
Q14
V
CC
Q15
PN PACKAGE
(TOP VIEW)
NC – No internal connection
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT781 1 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT781 1 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts or requests) to their respective system
clock.
The SN74ACT7811 is characterized for operation from 0°C to 70°C.
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
3
1
29
30
31
5
4
&
RDCLK
14
D10
13
D11
12
D12
11
D13
10
D14
9
D15
8
D16
17
7
D17
RESET
WRTCLK
WRTEN1
WRTEN2
RDCLK
RDEN1
RDEN2
&
RDEN
WRTCLK
EN1
2
OE
0
26
D0
25
D1
24
D2
23
D3
22
D4
21
D5
20
D6
19
D7
17
D8
15
D9
WRTEN
Data
Q0
38
0
Q1
39
Q2
41
Q3
42
Q4
44
IR
35
IN RDY
HF
36
HALF FULL
AF/AE
33
ALMOST FULL/EMPTY
OR
66
OUT RDY
Q15
61
Q16
63
Q17
64
17
Q5
46
Q6
47
Q7
49
Q8
50
Q9
52
Q10
53
Q11
55
Q12
56
Q13
58
Q14
59
1
DEF ALMOST FULL
27
Φ
FIFO 1024 × 18
SN74ACT7811
DAF
RESET
Data
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Write
Read
Location 1
Location 2
Location 1024
Location 1023
Pointer
Pointer
Synchronous
Synchronous
Write
Control
Read
Control
Reset
Logic
OE
D0 – D17
WRTCLK
WRTEN1
WRTEN2
Q0 – Q17
OR
IR
AF/AE
HF
RDCLK
RDEN1
RDEN2
Flag
Status-
Logic
DAF
Register
RESET
1024 × 18 RAM
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
†
NAME NO.
I/O
DESCRIPTION
Almost-full/almost-empty flag. The AF/AE boundary is defined by the almost-full/almost-empty offset
value (X). This value can be programmed during reset or the default value of 256 can be used. AF/AE
is high when the FIFO contains (X + 1) or less words or (1025 – X) or more words. AF/AE is low when
the FIFO contains between (X +2) and (1024 - X) words.
Programming procedure for AF/AE – The almost-full/almost-empty flag is programmed during each
reset cycle. The almost-full/almost-empty offset value (X) is either a user-defined value or the default
of X = 256. Instructions to program AF/AE using both methods are as follows:
AF/AE 33 O
User-defined X
AF/AE
33
O
Step 1:
Take DAF
from high to low.
Step 2:
If RESET is not already low, take RESET low.
Step 3:
With DAF held low, take RESET high. This defines the AF/AE using X.
Step 4:
To retain the current offset for the next reset, keep DAF low.
Default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
DAF 27 I
Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the
almost-full/almost-empty offset value (X). With DAF
held low, a low pulse on RESET defines the
AF/AE flag using X.
D0–D17
26–19, 17, 15–7 I
Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0– D8 also carry the
almost-full/almost-empty offset value (X) on a high-to-low transition of the DAF
.
HF 36 O
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
or less words.
IR 35 O
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven low on the rising edge of the second WRTCLK pulse. IR is then driven high on the rising edge
of the second WRTCLK pulse after RESET
goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
OE 2 I
Output enable. The data-out (Q0–Q17) outputs are in the high-impedance state when OE is low. OE
must be high before the rising edge of RDCLK to read a word from memory.
OR 66 O
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising
edge of the first RDCLK pulse after the last word is read.
Q0–Q17
38–39, 41–42, 44,
46–47, 49–50,
52–53, 55–56,
58–59, 61, 63–64
O
Data outputs. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge
of the third RDCLK pulse to occur after the first valid write. The RDEN1 and RDEN2 inputs do not
affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2,
OE, and the OR are high.
RDCLK 5 I
Read clock. Data is read out of memory on a low-to-high transition RDCLK if OR, OE, and RDEN1
and RDEN2 control inputs are high. RDCLK is a free-running clock and functions as the
synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
RDEN1,
RDEN2
4
3
I
Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.
RESET 1 I
A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and OR, HF, and
IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF
at a low level, a low
pulse on RESET
defines the AF/AE status flag using the almost-full/almost-empty offset value (X),
where X is the value previously stored. With DAF
at a high level, a low-level pulse on RESET defines
the AF/AE flag using the default value of X = 256.
†
Terminals listed are for the FN package.
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
†
NAME NO.
I/O
DESCRIPTION
WRTCLK 29 I
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and
WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
WRTEN1,
WRTEN2
30
31
I
Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word
to be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the
almost-full/almost-empty offset value (X).
†
Terminals listed are for the FN package.
ОООООООО
12341
2
1234
Invalid
WRTCLK
WRTEN1
WRTEN2
D0 – D17
RDCLK
RDEN1
RDEN2
Q0 – Q17
OR
AF/AE
IR
Store the Value of D0–D8 as X
Define the AF/AE Flag Using the
Value of X
HF
OE
X
†
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
RESET
DAF
1
0
†
X is the binary value of D0–D8 only.
Figure 1. Reset Cycle: Define AF/AE Using the Value of X
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