Datasheet SN74ACT7805-25DLR, SN74ACT7805-40DL, SN74ACT7805-40DLR, SN74ACT7805-15DL, SN74ACT7805-15DLR Datasheet (Texas Instruments)

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

D17
D16
D15
D14
D13
D12

D1 1

D10

V

CC

D9
D8

GND

D7
D6
D5
D4
D3
D2
D1
D0
HF

PEN

AF/AE

IR

DL PACKAGE

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

OE1
Q17
Q16
Q15
GND
Q14
V

CC

Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V

CC

Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR

D

Member of the Texas Instruments
Widebus Family

D

Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident

D

Read and Write Operations Synchronized
to Independent System Clocks

D

Input-Ready Flag Synchronized to Write
Clock

D

Output-Ready Flag Synchronized to Read
Clock

D

256 Words by 18 Bits

D

Low-Power Advanced CMOS Technology

D

Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag

D

Bidirectional Configuration and Width
Expansion Without Additional Logic

D

Fast Access Times of 12 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously

D

Data Rates up to 67 MHz

D

Pin-to-Pin Compatible With SN74ACT7803
and SN74ACT7813

D

Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing

description

The SN74ACT7805 is a 256-word ×18-bit clocked

RESET

WRTCLK
WRTEN2
WRTEN1

FIFO suited for buffering asynchronous data
paths up to 67-MHz clock rates and 12-ns access
times. Two devices can be configured for bidirectional data buf fering without additional logic. Multiple distributed
V

and GND pins, along with Texas Instruments patented output edge control (OEC) circuit, dampen

CC

simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2
Data is read from memory on the rising edge of RDCLK when RDEN

, OE1, and OE2 are low and OR is high.

The first word written to memory is clocked through to the output buffer , regardless of the RDEN

is low, and IR is high.

, OE1, and OE2

levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET

must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE)
flag high. The FIFO must be reset upon power up.

The SN74ACT7805 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and OEC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN74ACT7805
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

logic symbol

†

RESET

WRTCLK

WRTEN1
WRTEN2

RDCLK

OE1
OE2

RDEN

PEN

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16

D17

1
25
27

26
32
56

30

31
23

21
20
19
18
17
16
15
14
12

11
9
8
7
6
5
4
3

2

Φ

FIFO 256 × 18

RESET

WRTCLK

&

RDCLK

&

&

PROGRAM ENABLE

0

17

SN74ACT7805

WRTEN

ALMOST FULL/EMPTY

EN1

RDEN

Data

HALF-FULL

Data

IN RDY

OUT RDY

1

17

28

IR

22

HF

24

AF/AE

29

OR

33

0

34
36
37
38
40
41
42
43

45
46
47
48
49
51
53
54

55

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16

Q17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

OE1
OE2

D0–D17

RDCLK

RDEN

WRTCLK

WRTEN1
WRTEN2

RESET

PEN

Output

Control

Synchronous

Read

Control

Synchronous

Write

Control

Reset
Logic

Read

Pointer

Write

Pointer

Status-

Flag

Logic

Location 1
Location 2

256 × 18 RAM

Location 255
Location 256

Register

Q0–Q17

OR
IR
HF
AF/AE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ACT7805

I/O

DESCRIPTION

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

Terminal Functions

TERMINAL

NAME NO.

Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE, or the default

AF/AE 24 O

D0–D17
HF 22 O Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset.

IR 28 O

OE1, OE2 56, 30 I

OR 29 O

PEN

Q0–Q17

RDCLK 32 I

RDEN

RESET

WRTCLK 25 I

WRTEN1,
WRTEN2

21–14, 12–1 1,

9–2

23 I

33–34, 36–38,
40–43, 45–49,

51, 53–55

31 I

1 I

27, 26 I

value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is
high when memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset.

I 18-bit data input port

Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the
FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high
transition of WRTCLK after reset.

Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on
a low-to-high transition of RDCLK. When either OE1
outputs are in the high-impedance state.

Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is
low during reset and goes high on the third low-to-high transition of RDCLK after the first word is
loaded to empty memory .

Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D6
is latched as an AF/AE offset value when PEN

18-bit data output port. After the first valid write to empty memory , the first word is output on Q0–Q17
on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When

O

OR is low, the last word read from the FIFO is present on Q0–Q17.
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A

low-to-high transition of RDCLK reads data from memory when OE1
OR is high. OR is synchronous to the low-to-high transition or RDCLK.

Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on
the low-to-high transition of RDCLK.

Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of
WRTCLK must occur while RESET

Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
low-to-high transition of WRTCLK writes data to memory when WRTEN2
and IR is high. IR is synchronous to the low-to-high transition of WRTCLK.

Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO
on a low-to-high transition of WRTCLK.

is low. This sets HF, IR, and OR low and AF/AE high.

or OE2 is high, reads are disabled and the data

is low and WRTCLK is high.

, OE2, and RDEN are low and

is low, WRTEN1 is high,

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

RESET

PEN

WRTCLK

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

RDEN

1
0

123412

Don’t Care

Don’t Care

Don’t Care

1234

Don’t Care

Don’t Care

OE2

Q0–Q17

OR

AF/AE

HF

IR

Don’t Care

Invalid

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Define the AF/AE Flag Using the

Default Value of X = Y = 32

Figure 1. Reset Cycle

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN74ACT7805
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

RESET

PEN

WRTCLK

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

RDEN

1
0

1
0

1
0

W1 W2 W3 W4 W(X+2) W129 W(257–Y) W257

123

1
0

1
0

OE2

Q0–Q17

OR

AF/AE

HF

IR

Invalid

1
0

W1

Figure 2. Write

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

RESET

PEN

WRTCLK

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

W257

1
0

1
0

1

2

1
0

1
0

RDEN

OE2

Q0–Q17

OR

AF/AE

HF

W1 W2 W3 W(Y+1) W(Y+2) W129 W(256–X) W(257–X) W256 W257

IR

W130

Figure 3. Read

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN74ACT7805
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

offset values for AF/AE

The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the
offsets are not programmed, the default values of X = Y = 32 are used. The AF/AE flag is high when the FIFO
contains X or fewer words or (256 – Y) or more words.

Program enable (PEN

) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low . On the following low-to-high transition of WRTCLK, the binary value on D0–D6 is
stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN

low for another
low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D6 at the time of the second
WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are
disabled regardless of the state of the write enables (WRTEN1, WRTEN2
programmed for either X or Y (see Figure 4). To use the default values of X = Y = 32, PEN

RESET

WRTCLK

D0–D6

WRTEN1

34

PEN

X and Y Y

IR

). A maximum value of 127 can be

must be held high.

WRTEN2

Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

8

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

†

UNIT

IOLLow-level output current

mA

V

V

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

recommended operating conditions

’ACT7805-15 ’ACT7805-20 ’ACT7805-25 ’ACT7805-40

MIN MAX MIN MAX MIN MAX MIN MAX

V
V
V
I

OH

T

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V

I

I

I

OZ

I

CC

∆I
C
C

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 2 2 V

IH

Low-level input voltage 0.8 0.8 0.8 0.8 V

IL

High-level output current Q outputs, flags –8 –8 –8 –8 mA

p

Operating free-air temperature 0 70 0 70 0 70 0 70 °C

A

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

OH

Flags VCC = 4.5 V, IOL = 8 mA 0.5

OL

Q outputs VCC = 4.5 V, IOL = 16 mA 0.5

‡

CC
i
o

VCC = 4.5 V, IOH = –8 mA 2.4 V

VCC = 5.5 V, VI = VCC or 0 ±5 µA
VCC = 5.5 V, VO = VCC or 0 ±5 µA
VI = VCC – 0.2 V or 0 400 µA
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
VI = 0, f = 1 MHz 4 pF
VO = 0, f = 1 MHz 8 pF

Q outputs 16 16 16 16
Flags 8 8 8 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

SN74ACT7805

UNIT

tsuSetu time

ns

thHold time

ns

PARAMETER

UNIT

t

ns

AF/AE

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

timing requirements over recommended operating conditions (unless otherwise noted) (see
Figures 1 through 5)

’ACT7805-15 ’ACT7805-20 ’ACT7805-25 ’ACT7805-40

MIN MAX MIN MAX MIN MAX MIN MAX

f

clock

t

w

†

To permit the clock pulse to be utilized for reset purposes

Clock frequency 67 50 40 25 MHz

WRTCLK high or low 6 7 8 12

Pulse duration

p

RDCLK high or low
PEN low 8 9 9 12
D0–D17 before WRTCLK↑ 4 5 5 5
WRTEN1, WRTEN2

before WRTCLK↑
OE1, OE2 before RDCLK↑ 5 5 6 6
RDEN before RDCLK↑ 4 5 5 5
Reset: RESET low before first

WRTCLK↑ and RDCLK↑
PEN before WRTCLK↑ 5 6 6 6
Define AF/AE: PEN

before WRTCLK↑
D0–D17) after WRTCLK↑ 0 0 0 0
WRTEN1, WRTEN2

after WRTCLK↑
OE1, OE2, RDEN after RDCLK↑ 0 0 0 0
Reset: RESET low after fourth

WRTCLK↑ and RDCLK↑
Define AF/AE: PEN

after WRTCLK↑

†

†

6 7 8 12

4 5 5 5

5 6 6 6

5 6 6 6

0 0 0 0

2 2 2 2

2 2 2 2

ns

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

f

max

t

pd

‡

t

pd

pd

t

PLH

t

PHL

t

PLH

t

PHL

t

en

t

dis

‡

This parameter is measured with a 30-pF load (see Figure 6).

= 50 pF (unless otherwise noted) (see Figure 5)

L

FROM TO

(INPUT) (OUTPUT)

WRTCLK or

RDCLK
RDCLK↑ Any Q 4 9.5 12 4 13 4 15 4 20 ns
RDCLK↑ Any Q 8.5 ns

WRTCLK↑ IR 3 8.5 3 11 3 13 3 15

RDCLK↑ OR 3 8.5 3 11 3 13 3 15

WRTCLK↑

RDCLK↑

WRTCLK↑ HF 7 15 7 17 7 19 7 21 ns

RDCLK↑ HF 7 15.5 7 18 7 20 7 22 ns

RESET low
RESET low

OE1, OE2
OE1, OE2

AF/AE 2 9 2 11 2 13 2 15 ns

HF 2 10 2 12 2 14 2 16 ns
Any Q 2 8.5 2 11 2 11 2 11 ns
Any Q 2 9.5 2 11 2 14 2 14 ns

’ACT7805-15 ’ACT7805-20 ’ACT7805-25 ’ACT7805-40

MIN TYP†MAX MIN MAX MIN MAX MIN MAX

67 50 40 25 MHz

7 16.5 7 19 7 21 7 23
7 17 7 19 7 21 7 23

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF

pd

PARAMETER MEASUREMENT INFORMATION

7 V

SN74ACT7805

SCAS201B – MARCH 1991 – REVISED APRIL 1998

From Output

Timing

Input

Data

Input

Input

Output

Under Test

CL = 50 pF

(see Note A)

t

PLH

S1

500 Ω

LOAD CIRCUIT

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

h

500 Ω

Test
Point

t

PHL

3 V

0 V

3 V

0 V

3 V

0 V

V

V

OH

OL

Input

Output

Control

Output

Waveform 1

S1 at 7 V

Output

Waveform 2

S1 at Open

PARAMETER S1

t

t

t

t

1.5 V 1.5 V

t

PZL

t

PZH

ENABLE AND DISABLE TIMES

PZH

en

t

PZL

t

PHZ

dis

t

PLZ

t

PLH

pd

t

PHL

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

1.5 V

VOLTAGE WAVEFORMS

t

PLZ

t

PHZ

Closed

Closed

t

w

Open

Open

Open
Open

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

≈ 3.5 V

V

OL

V

OH

≈ 0 V

NOTE A: CL includes probe and jig capacitance.

Figure 5. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

SN74ACT7805
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

TYPICAL CHARACTERISTICS

typ + 8

typ + 6

typ + 4

typ + 2

– Propagation Delay Time – ns

pd

t

typ – 2

typ

VCC = 5 V
TA = 25°C
RL = 500 Ω

0

PROPAGATION DELAY TIME

vs

LOAD CAPACITANCE

50 100 200 250150 300

CL – Load Capacitance – pF

Figure 6

200

TA = 75°C

180

CL = 0 pF

160

140

120

100

80

– Supply Current – mA

60

CC(f)

I

40
20

0

010203040

f

clock

SUPPLY CURRENT

vs

CLOCK FREQUENCY

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

50 60 70

– Clock Frequency – MHz

Figure 7

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ACT7805

256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS201B – MARCH 1991 – REVISED APRIL 1998

APPLICATION INFORMATION

CLOCK A

W/R

CSA

A0–A17

SN74ACT7805

WRTCLK

A

18

WRTEN1
WRTEN2

D0–D17

SN74ACT7805

RDCLK
OE1
RDEN

OE2

Q0–Q17

RDCLK

OE1

RDEN

OE2

Q0–Q17

WRTCLK

WRTEN1

WRTEN2

D0–D17

18

CLOCK B
W/R

B

CSB

B0–B17

Figure 8. Bidirectional Configuration

WRTCLK

WRTEN1

WRTEN2

D0–D35

IR

36

SN74ACT7805

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

SN74ACT7805

WRTCLK

WRTEN1

WRTEN2

IR

D0–D17

RDCLK

RDEN

OE1

OE2

Q0–Q17

RDCLK

RDEN

OE1

OE2

Q0–Q17

RDCLK

OE1

OR

OE2

OR

OR

36

Q0–Q35

Figure 9. Word-Width Expansion: 256 × 36 Bits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated