Datasheet SN74ACT7804-20DL, SN74ACT7804-20DLR, SN74ACT7804-25DL, SN74ACT7804-25DLR, SN74ACT7804-40DL Datasheet (Texas Instruments)

SN74ACT7804

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

D

Member of the Texas Instruments
Widebus Family

D

Load Clock and Unload Clock Can Be
Asynchronous or Coincident

D

512 Words by 18 Bits

D

Low-Power Advanced CMOS Technology

D

Full, Empty, and Half-Full Flags

D

Programmable Almost-Full/Almost-Empty
Flag

D

Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously

D

Data Rates up to 50 MHz

D

3-State Outputs

D

Pin-to-Pin Compatible With SN74ACT7806
and SN74ACT7814

D

Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing

description

A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7804 is a
512-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.

Data is written into memory on a low-to-high
transition at the load-clock (LDCK) input and is
read out on a low-to-high transition at the
unload-clock (UNCK) input. The memory is full
when the number of words clocked in exceeds the
number of words clocked out by 512. When the
memory is full, LDCK signals have no effect on the
data residing in memory. When the memory is
empty, UNCK signals have no effect.

DL PACKAGE

(TOP VIEW)

RESET

GND

AF/AE

LDCK

FULL

NC – No internal connection

D17
D16
D15
D14
D13
D12

D1 1

D10

V

CC

D9
D8

D7
D6
D5
D4
D3
D2
D1
D0
HF

PEN

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OE
Q17
Q16
Q15
GND
Q14
V
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY

CC

CC

Status of the FIFO memory is monitored by the full (FULL
almost-full/almost-empty (AF/AE) flags. The FULL
memory is not full. The EMPTY

output is low when the memory is empty and high when it is not empty . The HF

output is low when the memory is full and high when the

), empty (EMPTY), half-full (HF), and

output is high when the FIFO contains 256 or more words. The AF/AE status flag is a programmable flag. The
first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value
(X) and the almost-full offset value (Y) if program enable (PEN

) is low. The AF/AE flag is high when the FIFO
contains X or fewer words or (512 – Y) or more words. The AF/AE flag is low when the FIFO contains between
(X + 1) and (511 – Y) words.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

description (continued)

A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY
power up.

low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon

The first word loaded into empty memory causes EMPTY

to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE

) input is high.

The SN74ACT7804 is characterized for operation from 0°C to 70°C.

logic symbol

†

Φ

FIFO 512 × 18

SN74ACT7804

ALMOST FULL/EMPTY

Data

Data

FULL

HALF-FULL

EMPTY

1

17

28

FULL

22

HF

24

AF/AE

29

EMPTY

33

0

34
36
37
38
40
41
42
43

45
46
47
48
49
51
53
54

55

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16

Q17

RESET

LDCK

UNCK

OE

PEN

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16

D17

1
25

32
56

23

21
20
19
18
17
16
15
14
12

11
9
8
7
6
5
4
3

2

RESET

LDCK
UNCK

EN1
PROGRAM ENABLE

0

17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

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I/O

DESCRIPTION

functional block diagram

OE

D0–D17

UNCK

Read

Pointer

SN74ACT7804

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

Location 1
Location 2

512 × 18 SRAM

LDCK

RESET

PEN

Write

Pointer

Reset
Logic

Status-

Flag

Logic

Location 511

Location 512

Q0–Q17

EMPTY
FULL

HF
AF/AE

Terminal Functions

TERMINAL

NAME NO.

Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value

AF/AE 24 O

D0–D17
EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.

FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 O Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.

PEN

Q0–Q17

RESET
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

2–9, 11–12,

14–21

23 I

33–34, 36–38,
40–43, 45–49,

51, 53–55

1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.

of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or fewer words or (512 – Y) or more words. AF/AE is high after reset.

I 18-bit data input port

Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN

O 18-bit data output port

is low and LDCK is high.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

offset values for AF/AE

The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value
(Y). They can be programmed after the FIFO is reset and before the first word is written to memory . The AF/AE
flag is high when the FIFO contains X or fewer words or (512 – Y) or more words.

To program the offset values, PEN

can be brought low after reset only when LDCK is low. On the following
low-to-high transition of LDCK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and
the almost-full offset value (Y). Holding PEN

low for another low-to-high transition of LDCK reprograms Y to the
binary value on D0–D7 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are
disabled while the offsets are programmed. A maximum value of 255 can be programmed for either X or Y (see
Figure 1). To use the default values of X = Y = 64, PEN

RESET

LDCK

PEN

D0–D7

EMPTY

Don’t Care

X and Y Y

must be held high.

Don’t Care

Figure 1. Programming X and Y Separately

4

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ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

ÏÏ

RESET

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PEN

LDCK

D0–D17

UNCK

OE

Q0–Q17

EMPTY

AF/AE

HF

FULL

W1 W2 W256

W

(X+1)

W

(512–Y)

W512

W2 W257 W258

(Y+1)W(Y+2)

1
0

Don’t Care

1
0

W

(512–X)W(513–X)

W

W511 W512W1

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

5

Define the AF/AE Flag Using
the Default Value of X and Y

Figure 2. Write, Read, and Flag Timing Reference

SN74ACT7804

SN74ACT7804

UNIT

IOLLow-level output current

mA

V

V

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

’ACT7804-20 ’ACT7804-25 ’ACT7804-40

MIN MAX MIN MAX MIN MAX

V
V
V
I

T

OH

Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 2 V

IH

Low-level input voltage 0.8 0.8 0.8 V

IL

High-level output current Q outputs, flags –8 –8 –8 mA

p

Operating free-air temperature 0 70 0 70 0 70 °C

A

Q outputs 16 16 16
Flags 8 8 8

†

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

OH

Flags VCC = 4.5 V, IOL = 8 mA 0.5

OL

Q outputs VCC = 4.5 V, IOL = 16 mA 0.5

I

I

I

OZ

I

CC

§

∆I

CC

C

i

C

o

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

This is the supply current for each input that is at one of the specified TTL voltage levels rather 0 V or VCC.

VCC = 4.5 V, IOH = –8 mA 2.4 V

VCC = 5.5 V, VI = VCC or 0 ±5 µA
VCC = 5.5 V, VO = VCC or 0 ±5 µA
VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
VI = 0, f = 1 MHz 4 pF
VO = 0, f = 1 MHz 8 pF

6

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UNIT

twPulse duration

ns

thHold time

ns

PARAMETER

UNIT

t

Any Q

ns

EMPTY

PHL

t

FULL

ns

t

AF/AE

ns

t

ns

t

HF

ns

SN74ACT7804

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

timing requirements over recommended operating conditions (see Figures 1 through 3)

’ACT7804-20 ’ACT7804-25 ’ACT7804-40

MIN MAX MIN MAX MIN MAX

f

clock

t

su

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

This parameter is measured at CL = 30 pF (see Figure 4).

Clock frequency 50 40 25 MHz

LDCK high or low 7 8 12
UNCK high or low 7 8 12
PEN low 7 8 12
RESET low 10 10 12
D0–D17 before LDCK↑ 5 5 5

Setup time

f

max

pd

‡

t

pd

t

PLH

t

PHL

PLH

pd

PLH

PHL

t

en

t

dis

= 50 pF (unless otherwise noted) (see Figure 3)

L

FROM TO

(INPUT) (OUTPUT)

LDCK or UNCK 50 40 25 MHz

LDCK↑
UNCK↑
UNCK↑ Any Q 10.5 ns

LDCK↑
UNCK↑

RESET low

LDCK↑
UNCK↑

RESET low

LDCK↑
UNCK↑

RESET low AF/AE 2 10 2 12 2 14

LDCK↑ HF 5 18 5 20 5 22
UNCK↑

RESET low

OE
OE

PEN before LDCK↑ 5 5 5
LDCK inactive before RESET high 5 6 6
D0–D17 after LDCK↑ 0 0 0
LDCK inactive after RESET high 5 6 6
PEN low after LDCK↑ 3 3 3
PEN high after LDCK↓ 0 0 0

’ACT7804-20 ’ACT7804-25 ’ACT7804-40

MIN TYP†MAX MIN MAX MIN MAX

9 20 9 22 9 24
6 11.5 15 6 18 6 20

EMPTY

FULL

Any Q 2 9 2 10 2 11 ns
Any Q 2 10 2 11 2 12 ns

6 15 6 17 6 19 ns
6 15 6 17 6 19
4 16 4 18 4 20
6 15 6 17 6 19
6 15 6 17 6 19
4 18 4 20 4 22
7 18 7 20 7 22
7 18 7 20 7 22

7 18 7 20 7 22
3 12 3 14 3 16

ns

ns

operating characteristics, VCC = 5 V, TA = 25°CFigure 2

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF

pd

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7

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

PARAMETER MEASUREMENT INFORMATION

7 V

From Output

Under Test

Timing

Input

Data

Input

Input

t

PLH

Output

S1

CL = 50 pF

(see Note A)

LOAD CIRCUIT

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

500 Ω

1.5 V

t

PARAMETER S1

t

t

Test
Point

500 Ω

3 V

0 V

h

3 V

0 V

3 V

0 V

t

PHL

V

OH

V

OL

Input

Output

Control

Output

Waveform 1

S1 at 7 V

Output

Waveform 2

S1 at Open

t

t

1.5 V 1.5 V

t

PZL

t

PZH

ENABLE AND DISABLE TIMES

PZH

en

t

PZL

t

PHZ

dis

t

PLZ

t

PLH

pd

t

PHL

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

VOLTAGE WAVEFORMS

t

PLZ

t

PHZ

1.5 V

Open

Closed

Open

Closed

Open
Open

t

w

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

≈ 3.5 V

V

OL

V

OH

≈ 0 V

NOTE A: CL includes probe and jig capacitance.

Figure 3. Load Circuit and Voltage Waveforms

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ACT7804

512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

TYPICAL CHARACTERISTICS

typ + 8

typ + 6

typ + 4

typ + 2

– Propagation Delay Time – ns

pd

t

typ – 2

typ

VCC = 5 V
TA = 25°C
RL = 500 Ω

0

PROPAGATION DELAY TIME

vs

LOAD CAPACITANCE

50 100 200 250150 300

CL – Load Capacitance – pF

Figure 4

200

TA = 75°C

180

CL = 0 pF

160

140

120

100

80

– Supply Current – mA

60

CC(f)

I

40
20

0

010203040

f

clock

SUPPLY CURRENT

vs

CLOCK FREQUENCY

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

50 60 70

– Clock Frequency – MHz

Figure 5

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9

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS204C – APRIL 1992 – REVISED APRIL 1998

APPLICATION INFORMATION

SN74ACT7804

LDCK

LDCK

UNCK

UNCK

FULL

D18–D35

D0–D17

FULL

D0–D17

SN74ACT7804

LDCK

FULL

D0–D17

EMPTY

OE

Q0–Q17

UNCK

EMPTY

OE

Q0–Q17

Figure 6. Word-Width Expansion: 512 × 36 Bits

EMPTY

OE

Q18–Q35

Q0–Q17

10

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