Datasheet SN74ACT7802-25FN, SN74ACT7802-25PN, SN74ACT7802-40FN, SN74ACT7802-40PN, SN74ACT7802-60FN Datasheet (Texas Instruments)
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SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
D
Member of the Texas Instruments
Widebus Family
D
Low-Power Advanced CMOS Technology
D
Load and Unload Clocks Can Be
Asynchronous or Coincident
D
1024 Words × 18 Bits
D
Programmable Almost-Full/Almost-Empty
Flag
D
Empty, Full, and Half-Full Flags
FN PACKAGE
(TOP VIEW)
D
Fast Access Times of 30 ns With a 50-pF
Load
D
Fall-Through Time Is 20 ns Typical
D
Data Rates up to 40 MHz
D
High-Output Drive for Direct Bus Interface
D
3-State Outputs
D
Package Options Include 68-Pin (FN) and
80-Pin Thin Quad Flat (PN) Packages
D17
D15
D16
D14
D13
D12
D1 1
D10
D9
V
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
NC – No internal connection
87 65493
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29
27
DAF
GND
LDCK
30
GND
UNCKNCNCOERESET
168672
31 32 33 34
CC
NC
NC
V
35 36 37 38 39
GND
AF/AE
V
HF
FULL
CC
GND
66 65
CC
V
CC
EMPTY
V
64 63 62 61
40 41 42 43
Q0
Q1
Q17
GND
Q16
Q2
GND
Q15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Q3
V
CC
V
CC
Q14
Q13
GND
Q12
Q11
V
CC
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
PN PACKAGE
(TOP VIEW)
NC
GND
GND
Q16
Q17
V
CC
EMPTY
GND
V
CC
RESET
OE
NC
NC
UNCK
GND
D17
D16
D15
NC
NC
CC
Q15
V
79 78 77 76 7580 74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
21
Q14
Q13
25 26 27 28
24
GND
GND
Q12
CC
Q11
V
72 71 7073
30 31 32 33
29
Q10
Q9
69 68
Q8
GND
67 66 65 64
34 35 36 37
Q7
V
CC
Q6
Q5
GND
63 62 61
38 39 40
GND
Q4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
CC
V
CC
NC
Q3
Q2
GND
Q1
Q0
V
CC
HF
FULL
GND
GND
AF/AE
V
CC
NC
NC
LDCK
GND
NC
NC
D14
D13
NC – No internal connection
D12
D4D3D2
D6
D7
D9
D8
D10
V
CC
GND
D1 1
D5
D1
D0
DAF
NC
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.
Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.
A low level on the reset (RESET
almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY
to any specific logic level. The FIFO must be reset upon power up. The Q outputs are noninverting and are in
the high-impedance state when the output-enable (OE) input is low.
When writing to the FIFO after a reset pulse or when the FIFO is empty , the first active transition on LDCK drives
EMPTY
high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.
The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from 0°C to 70°C.
) input resets the FIFO internal clock stack pointers and sets full (FULL) high,
) low. The Q outputs are not reset
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
logic symbol
†
Φ
FIFO 1024 × 18
SN74ACT7802
OE
DAF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
14
13
12
11
10
9
8
7
1
29
5
2
27
26
25
24
23
22
21
20
19
17
15
RESET
LDCK
UNCK
EN1
DEF ALMOST FULL
0
17
ALMOST FULL/EMPTY
Data
HALF FULL
Data
FULL
EMPTY
1
17
35
FULL
36
HF
33
AF/AE
66
EMPTY
38
0
39
41
42
44
46
47
49
50
52
53
55
56
58
59
61
63
64
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
RESET
LDCK
UNCK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ACT7802
I/O
DESCRIPTION
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
functional block diagram
OE
D0–D17
LDCK
UNCK
RESET
DAF
Write
Control
Read
Control
Reset
Logic
Read
Pointer
Write
Pointer
Status-
Flag
Logic
Location 1
Location 2
1024 × 18 RAM
Location 1023
Location 1024
Q0–Q17
EMPTY
FULL
HF
AF/AE
Terminal Functions
TERMINAL
NAME NO.
AF/AE 33 O
DAF
D0–D17
EMPTY 66 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 35 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 36 O Half-full flag. HF is high when the FIFO memory contains 512 or more words. HF is low after reset.
LDCK 29 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 2 I Output enable. When OE is low, the data outputs are in the high-impedance state.
38–39, 41–42,
Q0–Q17
RESET
UNCK 5 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
†
Terminal numbers listed are for the FN package.
49–50, 52–53,
55–56, 58–59,
†
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 256 can be used for the almost-empty almost-full offset (X). AF/AE is high when memory contains X
or fewer words or (1024 – X) or more words. AF/AE is high after reset.
27 I
7–15, 17,
19–26
44, 46–47,
61, 63–64
1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.
Define almost-full flag. The high-to-low transition of DAF stores the binary value of data inputs as the
AF/AE offset value (X). With DAF held low , a low pulse on RESET defines AF/AE using X.
I 18-bit data input port
O 18-bit data-output port
4
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SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
offset value values for AF/AE
The FIFO memory status is monitored by the FULL, EMPTY , HF , and AF/AE flags. The FULL output is low when
the memory is full; the EMPTY
contains 512 or more words and low when it contains fewer than 512 words. The level of the AF/AE flag is
determined by both the number of words in the FIFO and a user-definable offset X. AF/AE is high when the FIFO
is almost full or almost empty , i.e., when it contains X or fewer words or (1024 – X) or more words. The AF/AE
offset value is either user-defined or the default value of 256; it is programmed during each reset cycle as follows:
user-defined X:
output is low when the memory is empty . The HF output is high when the memory
Take DAF
If RESET
With DAF
default X:
To redefine the AF/AE flag using the default value of X = 256, hold DAF
from high to low.
is not already low, take RESET low.
held low, take RESET high. This defines the AF/AE flag using X.
high during the reset cycle.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
6
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SCAS187D – AUGUST 1990 – REVISED APRIL 1998
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
RESET
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAF
LDCK
D0–D17
W1 W2 WX+1 W512
X
UNCK
OE
Q0–Q17
EMPTY
AF/AE
HF
FULL
Define the AF/AE Offset Value (X)
Using the Data on D0 – D8
W1
W1024–X
W1024
Don’t Care
Don’t Care
W2 WX+2 W513 W514 W1024–X W1025–X
WX+1
W1023 W1024
Define the AF/AE Offset Value (X)
Using the Default Value of 256
Figure 1. Write, Read, and Flag Timing Reference
UNIT
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
CC
I
Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 1): FN package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
PN package 62°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
’ACT7802-25 ’ACT7802-40 ’ACT7802-60
MIN MAX MIN MAX MIN MAX
V
V
V
I
I
T
OH
OL
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 2 V
IH
Low-level input voltage 0.8 0.8 0.8 V
IL
High-level output current –8 –8 –8 mA
Low-level output current 16 16 16 mA
Operating free-air temperature 0 70 0 70 0 70 °C
A
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
OH
V
OL
I
I
I
OZ
§
I
CC
§
∆I
CC
C
i
C
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
ICC tested with outputs open
o
VCC = 4.5 V, IOH = –8 mA 2.4 V
VCC = 4.5 V, IOL = 16 mA 0.5 V
VCC = 5.5 V, VI = VCC or 0 ±5 µA
VCC = 5.5 V, VO = VCC or 0 ±5 µA
VI = VCC – 0.2 V or 0 400 µA
VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 1 mA
VI = 0, f = 1 MHz 4 pF
VO = 0, f = 1 MHz 8 pF
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7
SN74ACT7802
UNIT
twPulse duration
ns
thHold time
ns
PARAMETER
UNIT
t
Any Q
ns
EMPTY
t
FULL
ns
t
AF/AE
ns
t
ns
t
HF
ns
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
timing requirements over recommended operating conditions (see Figures 1 and 2)
’ACT7802-25 ’ACT7802-40 ’ACT7802-60
MIN MAX MIN MAX MIN MAX
f
clock
t
su
Clock frequency 40 25 16.7 MHz
LDCK high or low 10 14 20
UNCK high or low 10 14 20
DAF high 10 10 10
RESET low 20 25 25
D0–D7 before LDCK↑ 4 5 5
RESET inactive (high) before LDCK↑ 5 5 5
Setup time
Define AF/AE: D0–D8 before DAF
Define AF/AE: DAF↓ before RESET↑ 7 7 7
Define AF/AE (default): DAF high before RESET↑ 5 5 5
D0–D7 after LDCK↑ 1 2 2
Define AF/AE: D0–D8 after DAF↓ 0 0 0
Define AF/AE: DAF low after RESET↑ 0 0 0
Define AF/AE (default): DAF high after RESET↑ 0 0 0
↓ 5 5 5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
f
max
pd
‡
t
pd
t
PLH
t
PHL
PLH
pd
PLH
PHL
t
en
t
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is measured with CL = 30 pF (see Figure 3).
dis
= 50 pF (see Figures 1 and 2)
L
FROM TO
(INPUT) (OUTPUT)
LDCK or UNCK 40 25 16.7 MHz
LDCK↑
UNCK↑
UNCK↑ Any Q 21 ns
LDCK↑
UNCK↑
RESET↓
LDCK↑ FULL 4 18 4 20 4 22
UNCK↑
RESET↓
LDCK↑
UNCK↑
RESET↓ AF/AE 2 17 2 19 2 21
LDCK↑ HF 2 18 2 20 2 22
UNCK↑
RESET↓
OE Any Q 2 12 2 14 2 16 ns
OE Any Q 2 14 2 16 2 18 ns
EMPTY
’ACT7802-25 ’ACT7802-40 ’ACT7802-60
MIN TYP†MAX MIN MAX MIN MAX
8 20 30 8 35 8 45
12 30 12 35 12 45
4 18 4 20 4 22 ns
2 18 2 20 2 22
2 18 2 20 2 22
4 17 4 19 4 21
2 17 2 19 2 21
2 20 2 22 2 24
2 20 2 22 2 24
2 18 2 20 2 22
2 17 2 19 2 21
ns
operating characteristics, VCC = 5 V, TA = 25°C
8
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per channel CL = 50 pF, f = 5 MHz 65 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timing
From Output
Under Test
CL = 50 pF
(see Note A)
Input
Data
Input
PARAMETER MEASUREMENT INFORMATIONFigure 1
7 V
S1
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
h
500 Ω
Test
Point
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
PARAMETER S1
3 V
0 V
3 V
0 V
Input
Output
Control
t
t
t
t
1.5 V 1.5 V
t
PZL
PZH
en
t
PZL
t
PHZ
dis
t
PLZ
t
PLH
pd
t
PHL
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLZ
t
w
Open
Closed
Open
Closed
Open
Open
3 V
0 V
3 V
1.5 V1.5 V
0 V
Input
t
PLH
Output
NOTE A: CL includes probe and jig capacitance.
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
3 V
0 V
V
V
OH
OL
Output
Waveform 1
S1 at 7 V
Output
Waveform 2
S1 at Open
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PHZ
1.5 V
VOL + 0.3 V
VOH – 0.3 V
≈ 3.5 V
V
OL
V
OH
≈ 0 V
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9
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
typ + 8
typ + 6
typ + 4
typ + 2
– Propagation Delay Time – ns
pd
t
typ – 2
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
VCC = 5 V
RL = 500 Ω
TA = 25°C
typ
0 50 100 150 200 250 300
CL – Load Capacitance – pF
Figure 3
POWER DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
typ + 3
typ + 2
typ + 1
typ – 1
– Power Dissipation Capacitance – pF
typ – 2
pd
C
typ – 3
f = 5 MHz
TA = 25°C
CL = 50 pF
typ
4.5 4.6 4.7 4.8 4.9 5 5.1
VCC – Supply Voltage – V
Figure 4
5.2 5.3 5.4 5.5
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
APPLICATION INFORMATION
LDCK UNCKLDCK
FULL
D18–D35
D0–D17
Figure 5. Word-Width Expansion: 1024 × 36 Bit
SN74ACT7802
FULL
D0–D17
SN74ACT7802
LDCK UNCK
FULL
D0–D17
EMPTY
OE
Q0–Q17
EMPTY
OE
Q0–Q17
UNCK
EMPTY
OE
Q18–Q35
Q0–Q17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
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performed, except those mandated by government requirements.
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