查询SN54ACT74供应商
SN54ACT74, SN74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
D
Inputs Are TTL-Voltage Compatible
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’ACT74 dual positive-edge-triggered devices
are D-type flip-flops.
A low level at the preset (PRE
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
The SN54ACT74 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ACT74 is characterized for
operation from –40°C to 85°C.
) or clear (CLR) input
and CLR are
SN54ACT74 ...J OR W PACKAGE
SN74ACT74 . . . D, DB, N, OR PW PACKAGE
1CLR
1CLK
1PRE
SN54ACT74 . . . FK PACKAGE
1CLK
NC
1PRE
NC
1Q
NC – No internal connection
(TOP VIEW)
1
1D
2
3
4
1Q
5
1Q
6
GND
7
(TOP VIEW)
1D
3212019
4
5
6
7
8
910111213
1Q
1CLR
NC
NC
GND
14
13
12
11
10
9
8
CC
V
2Q
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
2CLR
18
17
16
15
14
2Q
2D
NC
2CLK
NC
2PRE
PRE
L H X X H L
H LXXLH
L LXXH†H
H H ↑ HHL
H H ↑ LLH
H H L X Q
†
This configuration is unstable; that is, it does not
persist when either PRE
inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK D Q Q
or CLR returns to its
OUTPUTS
Q
0
†
0
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ACT74, SN74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
1PRE
1CLK
1D
1CLR
2PRE
2CLK
2D
2CLR
4
3
2
1
10
11
12
13
S
C1
1D
R
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
5
1Q
6
1Q
9
2Q
8
2Q
CLR
TG
C
D
C
C
C
C
C
TGTGTG
C
Q
Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ACT74, SN74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ACT74 SN74ACT74
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
CC
0 V
0 V
CC
CC
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT74, SN74ACT74
PARAMETER
TEST CONDITIONS
V
UNIT
I
50 µA
V
I
24 mA
V
I
50 µA
V
I
24 mA
V
UNIT
twPulse duration
ns
t
S
CLK↑
ns
(INPUT)
(OUTPUT)
MIN
MAX
PRE
CLR
Q
Q
ns
CLK
Q
Q
ns
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –
OH
OH
OL
I
I
I
CC
‡
∆I
CC
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
i
= –
OH
IOH = –50 mA
IOH = –75 mA
=
OL
=
OL
IOL = 50 mA
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
One input at 3.4 V ,
Other inputs at GND or V
VI = VCC or GND 5 V 3 pF
†
†
†
†
CC
4.5 V 4.4 4.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.86
5.5 V 3.85
4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
5.5 V 0.6 1.6 1.5 mA
TA = 25°C SN54ACT74 SN74ACT74
MIN TYP MAX MIN MAX MIN MAX
timing characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C SN54ACT74 SN74ACT74
MIN MAX MIN MAX MIN MAX
f
clock
su
t
h
Clock frequency 0 145 0 145 0 145 MHz
PRE or CLR low 5 7 6
CLK 5 7 6
etup time, data before
Hold time, data after CLK↑ 1 1 1 ns
Data 3 4 3.5
PRE or CLR inactive 0 0.5 0
switching characteristics over recommended operating free-air temperature (unless otherwise
noted) (see Figure 1)
SN54ACT74
TA = 25°C
1 5.5 9.5 1 11.5
1 6 10 1 12.5
1 7.5 11 1 14
1 6 10 1 12
UNIT
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
FROM
or
TO
MIN TYP MAX
145 210 85 MHz
or
or
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
MIN
MAX
PRE
CLR
Q
Q
ns
CLK
Q
Q
ns
SN54ACT74, SN74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature (unless otherwise
noted) (see Figure 1)
SN74ACT74
TA = 25°C
UNIT
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
FROM
or
TO
or
or
MIN TYP MAX
145 210 125 MHz
3 5.5 9.5 2.5 10.5
3 6 10 3 11.5
4 7.5 11 4 13
3.5 6 10 3 11.5
operating characteristics, V
C
Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF
pd
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Input
In-Phase
Output
Out-of-Phase
Output
t
PLH
t
PHL
VOLTAGE WAVEFORMS
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V 1.5 V
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
S1
50% V
CC
50% V
CC
= 25°C
A
2 × V
Open
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
CC
V
V
V
OH
OL
OH
OL
Input
Timing Input
Data Input
TEST S1
t
PLH/tPHL
1.5 V 1.5 V
VOLTAGE WAVEFORMS
t
su
1.5 V
VOLTAGE WAVEFORMS
t
w
Open
1.5 V
t
h
1.5 V
3 V
0 V
3 V
0 V
3 V
0 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Loading...