Texas Instruments SN74ACT564DBR, SN74ACT564DW, SN74ACT564DWR, SN74ACT564N, SN74ACT564PWLE Datasheet
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SN54ACT564, SN74ACT564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS549A – NOVEMBER 1995 – REVISED MA Y 1996
D
Inputs Are TTL-Voltage Compatible
D
EPIC
(Enhanced-Performance Implanted
SN54ACT564 ...J OR W PACKAGE
SN74ACT564 . . . DB, DW, N, OR PW P ACKAGE
(TOP VIEW)
CMOS) 1-µm Process
D
3-State Inverted Outputs Drive Bus Lines
Directly
D
Flow-Through Architecture to Optimize
PCB Layout
D
Full Parallel Access for Loading
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Ceramic (J) DIPs
SN54ACT564 . . . FK PACKAGE
description
The ’ACT564 are octal D-type edge-triggered
(TOP VIEW)
2D1DOE
V
CC
1Q
flip-flops that feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input,
the Q
outputs are set to the complements of the
logic levels set up at the data (D) inputs.
A buffered output-enable (OE
) input places the eight outputs in either a normal logic state (high or low logic
3D
4D
5D
6D
7D
3 2 1 20 19
4
5
6
7
8
910111213
8D
CLK
GND
8Q
18
17
16
15
14
7Q
2Q
3Q
4Q
5Q
6Q
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ACT564 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ACT564 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
OE CLK D
L ↑ H L
L ↑ LH
L H or L X Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
1
SN54ACT564, SN74ACT564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS549A – NOVEMBER 1995 – REVISED MA Y 1996
logic symbol
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
1D
C1
1
19
18
17
16
15
14
13
12
logic diagram (positive logic)
1
OE
11
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2
C1
1D
To Seven Other Channels
19
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
DW package 1.6 W. . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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