Texas Instruments SN74ACT3632-15PCB, SN74ACT3632-15PQ, SN74ACT3632-20PCB, SN74ACT3632-20PQ, SN74ACT3632-30PCB Datasheet

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SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

Mailbox-Bypass Register for Each FIFO

Programmable Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

IRA, ORA, AEA, and AFA Flags Synchronized by CLKA

IRB, ORB, AEB, and AFB Flags Synchronized by CLKB

Low-Power 0.8-µm Advanced CMOS T echnology

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 11 ns

Pin-to-Pin Compatible With the SN74ACT3622 and SN74ACT3642

Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

PCB PACKAGE

(TOP VIEW)

A35 A34 A33 A32

A31 A30

GND

A29 A28 A27 A26 A25 A24 A23

GND

A22

A21 A20 A19 A18

GND

A17 A16 A15 A14 A13

A12

B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 V

B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 V

B15 B14 B13 B12 GND

GND

CLKA

ENA

GND

A1 1

A10

CSA

IRA

ORA

MBA

AFA

FS0

GND

FS1

RST2

MBB

MBF1

AEB

ORB

IRB

W/RA

A7A6A5

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

CSB

W/RB

ENB

CLKB

B10

5556575859

RST1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

AEA

AFB

GND

B1 1

MBF2

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116 115 114 113 112

111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

5251 83828180797877767574737271706968676665646362616059585756555453

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

NC B35 B34 B33 B32

GND

B31 B30 B29 B28 B27 B26

B25 B24

GND

B23 B22 B21 B20 B19 B18

GND

B17 B16

B15 B14 B13 B12

GND

NC NC A35 A34 A33 A32 V

A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 V

A21 A20 A19 A18 GND A17 A16 A15 A14 A13 V

A12 NC

PQ PACKAGE

†

(TOP VIEW)

NCNCV

CLKB

ENB

W/RB

CSB

GND

IRB

ORB

AFB

AEB

MBF1

MBB

RST2

FS1

GND

FS0

RST1

MBA

MBF2

AEA

AFA

ORA

IRA

CSA

W/RA

ENA

CLKA

GND

B1 1

B10

B9B8B7

GND

B5B4B3B2B1

GND

A0A1A2

A3A4A5

GND

A6A7A8

A10

A1 1

GND

NC – No internal connection †

Uses Yamaichi socket IC51-1324-828

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The SN74ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags, almost full (AF

) and almost empty (AE) to indicate when a selected number of words is stored in memory . Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.

The SN74ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA

, AFB) flag of a FIFO are two-stage synchronized to the

port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA

, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array . Of fset values for the AF and AE flags of both FIFOs can be programmed from port A.

The SN74ACT3632 is characterized for operation from 0°C to 70°C. For more information on this device family, see the following application reports:

•

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

•

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors

(literature number

SCAA005)

•

Metastability Performance of Clocked FIFOs

(literature number SCZA004)

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Port-A

Control

Logic

CLKA

CSA

W/RA

ENA

MBA

FIFO1,

Mail1 Reset Logic

RST1

512 × 36

SRAM

Input Register

Output Register

Mail1

Write

Pointer

Read

Pointer

Status-Flag

Logic

Programmable-

Flag

Offset Registers

Status-Flag

Logic

Read

Pointer

Write

Pointer

512 × 36

SRAM

Input Register

Output Register

Mail2

Port-B

Control

Logic

IRA

AFA

FS0 FS1

A0–A35

ORA AEA

MBF2

FIFO2,

Mail2

Reset

Logic

MBF1

ORB AEB

B0–B35

IRB AFB

RST2

CLKB CSB

W/RB ENB MBB

FIFO1

FIFO2

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.

AEA

(port A)

Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2 is less than or equal to the value in the almost-empty A offset register, X2.

AEB

(port B)

Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1 is less than or equal to the value in the almost-empty B offset register, X1.

AFA

(port A)

Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in FIFO1 is less than or equal to the value in the almost-full A offset register , Y1.

AFB

(port B)

Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in FIFO2 is less than or equal to the value in the almost-full B offset register , Y2.

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA

, and AEA are all synchronized to the low-to-high transition of CLKA.

CLKB I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB

, and AEB are synchronized to the low-to-high transition of CLKB.

CSA

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0–A35 outputs are in the high-impedance state when CSA

is high.

CSB

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0–B35 outputs are in the high-impedance state when CSB

is high. ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1, FS0 I

Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0 or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO AF

and

flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2 go high, the

first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.

IRA

(port A)

Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA after reset.

IRB

(port B)

Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB after reset.

MBA I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output-register data for output.

MBB I

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO1 output-register data for output.

MBF1

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites to the mail1 register are inhibited while MBF1

is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B

read is selected and MBB is high. MBF1

is set high when FIFO1 is reset.

MBF2

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites to the mail2 register are inhibited while MBF2

is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A

read is selected and MBA is high. MBF2

is also set high when FIFO2 is reset.

ORA

(port A)

Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to empty memory.

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

I/O DESCRIPTION

ORB

(port B)

Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

RST1

FIFO1 reset. T o reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST1

is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset

selection. FIFO1 must be reset upon power up before data is written to its RAM.

RST2

FIFO2 reset. T o reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST2

is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset

selection. FIFO2 must be reset upon power up before data is written to its RAM.

W/RA

Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R

A is high.

W/RB

Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W

/RB is low.

detailed description

reset

The FIFO memories of the SN74ACT3632 are reset separately by taking their reset (RST1

, RST2) inputs low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA

, AEB) low,

and the almost-full flag (AFA

, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

A low-to-high transition on a FIFO reset (RST1

, RST2) input latches the value of the flag-select (FS0, FS1)

inputs for choosing the almost-full and almost-empty offset programming method.

almost-empty flag and almost-full flag offset programming

Four registers in the SN74ACT3632 are used to hold the offset values for the AE

and AF flags. The port-B

almost-empty flag (AEB

) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset register is

labeled X2. The port-A almost-full flag (AFA

) offset register is labeled Y1 and the port-B almost-full flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1).

T able 1. Flag Programming

FS1 FS0 RST1 RST2

X1 AND Y1 REGISTERS†X2 AND Y2 REGISTERS

‡

H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16 L H ↑ X 8 X L H X ↑ X 8 L L ↑ ↑ Programmed from port A Programmed from port A

†

X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

‡

X2 register holds the offset for AEA

; Y2 register holds the offset for AFB.

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

almost-empty flag and almost-full flag offset programming (continued)

To load the AE

flag and AF flag offset registers of a FIFO with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1

) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2

). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously

or at different times. To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0

and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A (A8–A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from 1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high and both FIFOs begin normal operation.

FIFO write/read operation

The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA

) and the port-A

write/read select (W/R

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0–A35 outputs are active when both CSA

and W/RA are low.

Data is loaded into FIFO1 from the A0–A35 inputs on a low-to-high transition of CLKA when CSA

is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA

is low, W/RA is low , ENA is high, MBA is low , and ORA is high (see T able 2). FIFO

reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

A0–A35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W

/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is

controlled by the port-B chip select (CSB

) and the port-B write/read select (W/RB). The B0–B35 outputs are

in the high-impedance state when either CSB

is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high. Data is loaded into FIFO2 from the B0–B35 inputs on a low-to-high transition of CLKB when CSB

is low, W/RB is low, ENB is high, MBB is low , and IRB is high. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of CLKB when CSB

is low, W/RB is high, ENB is high, MBB is low , and ORB is high (see T able 3). FIFO

reads and writes on port B are independent of any concurrent port-A operation.

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB CLKB

B0–B35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L L L X X In high-impedance state None L L H L ↑ In high-impedance state FIFO2 write L L H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L ↑ Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setup- and hold-time window of the cycle.

When a FIFO OR flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the OR flag high. When the OR flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port’s chip select, write/read select, enable, and mailbox select.

synchronized FIFO flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA

, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB

are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

Table 4. FIFO1 Flag Operation

NUMBER OF WORDS

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

IN FIFO1

†‡

ORB AEB AFA IRA

0 L L H H

1 to X1 H LHH

(X1 + 1) to [512 – (Y1 + 1)] H HHH

(512 – Y1) to 511 H HLH

512 H H L L

†

X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA

. Both X1 and Y1 are selected during a reset of

FIFO1 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

synchronized FIFO flags (continued)

Table 5. FIFO2 Flag Operation

NUMBER OF WORDS

SYNCHRONIZED

TO CLKA

SYNCHRONIZED

TO CLKB

IN FIFO2

†‡

ORA AEA AFB IRB

0 L L H H

1 to X2 H LHH

(X2 + 1) to [512 – (Y2 + 1)] H HHH

(512 – Y2) to 511 H HLH

512 H H L L

†

X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB

. Both X2 and Y2 are selected during a reset

of FIFO2 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

output-ready flags (ORA, ORB)

The OR flag of a FIFO is synchronized to the port clock that reads data from its array . When the OR flag is high, new data is present in the FIFO output register. When the OR flag is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the OR flag synchronizing clock; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register.

A low-to-high transition on an OR flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t

sk1

, or greater, after the write. Otherwise, the subsequent clock cycle can be the

first synchronization cycle (see Figures 7 and 8).

input-ready flags (IRA, IRB)

The IR flag of a FIFO is synchronized to the port clock that writes data to its array . When the IR flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the IR flag synchronizing clock; therefore, an IR flag is low if less than two cycles of the IR flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the IR flag synchronizing clock after the read sets the IR flag high.

A low-to-high transition on an IR flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t

sk1

, or greater, after the read. Otherwise, the subsequent clock cycle can be the

first synchronization cycle (see Figures 9 and 10).

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

almost-empty flags (AEA, AEB)

The AE flag of a FIFO is synchronized to the port clock that reads data from its array . The almost-empty state is defined by the contents of register X1 for AEB

and register X2 for AEA. These registers are loaded with preset

values during a FIFO reset or programmed from port A (see

almost-empty flag and almost-full flag offset

programming

). An AE flag is low when its FIFO contains X or fewer words and is high when its FIFO contains

(X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of the AE

flag synchronizing clock are required after a FIFO write for its AE flag to

reflect the new level of fill. Therefore, the AE

flag of a FIFO containing (X + 1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An AE

flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills

memory to the (X + 1) level. A low-to-high transition of an AE

flag synchronizing clock begins the first

synchronization cycle if it occurs at time t

sk2

, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12).

almost-full flags (AFA, AFB)

The AF flag of a FIFO is synchronized to the port clock that writes data to its array . The almost-full state is defined by the contents of register Y1 for AFA

and register Y2 for AFB. These registers are loaded with preset values

during a FIFO reset or programmed from port A (see

almost-empty flag and almost-full flag offset programming

An AF

flag is low when its FIFO contains (512 – Y) or more words and is high when its FIFO contains

[512 – (Y + 1)] or fewer words. A data word is present in the FIFO output register has been read from memory . Two low-to-high transitions of the AF

flag synchronizing clock are required after a FIFO read for its AF flag to

reflect the new level of fill. Therefore, the AF

flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An AF

flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [512 – (Y + 1)]. A low-to-high transition of an AF

flag synchronizing clock begins the first synchronization cycle if it occurs at time t

sk2

, or greater, after the read that reduces the number of words in memory to [512 – (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14).

mailbox registers

Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by CSA

, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB

writes B0–B35 data to the mail2 register when a port-B write is selected by CSB

, W/RB, and ENB and with MBB

high. Writing data to a mail register sets its corresponding flag (MBF1

or MBF2) low. Attempted writes to a mail

register are ignored while the mail flag is low. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port

mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1 register flag (MBF1

) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB,

/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on

CLKA when a port-A read is selected by CSA

, W/RA, and ENA and with MBA high. The data in a mail register

remains intact after it is read and changes only when new data is written to the register.

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

CLKB

RST1

0,1

h(FS)

su(FS)

h(RS)

su(RS)

FS1, FS0

IRA

pd(C-IR)

ORB

pd(C-OR)

pd(R-F)

AEB

AFA

MBF1

pd(R-F)

Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight

†

FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.

AEA Offset

(X2)

CLKA

RST1,

RST2

FS1, FS0

0,0

CLKB

IRB

pd(C-IR)

ENA

IRA

A0–A35

h(D)

su(D)

su(EN)

h(EN)

sk1

‡

su(FS)

h(FS)

pd(C-IR)

AFA Offset

(Y1)

AEB Offset

(X1)

AFB Offset

(Y2)

First Word to FIFO1

‡

sk1

is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time

between the rising edge of CLKA and rising edge of CLKB is less than t

sk1

, IRB may transition high one cycle later than shown.

NOTE A: CSA

= L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the AF Flag and AE Flag Offset Values After Reset

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

IRA

CSA

†

su(EN)

w(CLKL)

w(CLKH)

h(EN)

su(EN)

W/RA

MBA

ENA

A0–A35

†

su(EN)

h(EN)

su(EN)

h(EN)

su(EN)

h(EN)

su(D)

h(D)

h(EN)

No Operation

†

Written to FIFO1

Figure 3. Port-A Write-Cycle Timing for FIFO1

CLKB

IRB

CSB

‡

su(EN)

w(CLKL)

w(CLKH)

h(EN)

su(EN)

W/RB

MBB

ENB

B0–B35

†

su(EN)

h(EN)

su(EN)

h(EN)

su(EN)

h(EN)

su(D)

h(D)

h(EN)

No Operation

‡

Written to FIFO2

Figure 4. Port-B Write-Cycle Timing for FIFO2

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

ORA

CSA

W/RA

MBA

ENA

A0–A35

su(EN)

pd(M-DV)

†

w(CLKL)

w(CLKH)

h(EN)

†

dis

Operation

su(EN)

h(EN)

su(EN)

h(EN)

†

Read from FIFO2

Figure 5. Port-A Read-Cycle Timing for FIFO2

su(EN)

pd(M-DV)

CLKB

ORB

CSB

‡

w(CLKL)

w(CLKH)

h(EN)

W/RB

MBB

ENB

B0–B35

‡

dis

Operation

su(EN)

h(EN)

su(EN)

h(EN)

‡

Read from FIFO1

Figure 6. Port-B Read-Cycle Timing for FIFO1

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(EN)

CLKA

ORB

A0–A35

MBA

ENA

CSA

W/RA

IRA

CLKB

CSB

W/RB

MBB

ENB

B0–B35

h(EN)

su(EN)

ÎÎÎÎ

w(CLKH)

w(CLKL)

h(EN)

pd(C-OR)

Old Data in FIFO1 Output Register

123

Low

High

w(CLKL)

w(CLKH)

High

h(EN)

su(EN)

h(D)

su(D)

sk1

†

Low

High

Low

†

sk1

is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the

FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t

sk1

, the transition

of ORB high and load of the first word to the output register may occur one CLKB cycle later than shown.

Figure 7. ORB-Flag Timing and First Data-Word Fall-Through When FIFO1 Is Empty

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(EN)

CLKB

ORA

B0–B35

MBB

ENB

CSB

W/RB

IRB

CLKA

CSA

W/RA

MBA

ENA

A0–A35

h(EN)

su(EN)

w(CLKH)

w(CLKL)

h(EN)

pd(C-OR)

Old Data in FIFO2 Output Register

123

Low

w(CLKL)

w(CLKH)

h(EN)

su(EN)

h(D)

su(D)

sk1

†

Low

High

†

sk1

is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the

FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t

sk1

, the transition

of ORA high and load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA-Flag Timing and First Data-Word Fall-Through When FIFO2 Is Empty

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKB

IRA

B0–B35

MBB

ENB

CSB

W/RB

ORB

CLKA

CSA

W/RA

MBA

ENA

A0–A35

su(EN)

h(EN)

su(EN)

pd(C-IR)

FIFO1 Full

sk1

†

Previous Word in FIFO1 Output Register Next Word From FIFO1

w(CLKH)

w(CLKL)

To FIFO1

Low

High

Low

High

h(EN)

su(EN)

h(D)

su(D)

High

w(CLKH)

w(CLKL)

pd(C-IR)

†

sk1

is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

sk1

, IRA may transition high one CLKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIFO1 Is Full

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(EN)

h(EN)

CLKA

IRB

A0–A35

MBA

ENA

CSA

W/RA

ORA

CLKB

CSB

W/RB

MBB

ENB

B0–B35

w(CLKH)

su(EN)

h(EN)

su(EN)

pd(C-IR)

FIFO2 Full

sk1

†

Previous Word in FIFO2 Output Register Next Word From FIFO2

w(CLKH)

w(CLKL)

To FIFO2

Low

h(D)

su(D)

Low

High

w(CLKL)

pd(C-IR)

†

sk1

is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition high in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than t

sk1

, IRB may transition high one CLKB cycle later than shown.

Figure 10. IRB-Flag Timing and First Available Write When FIFO2 Is Full

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(EN)

LKA

AEB

ENB

ENA

h(EN)

su(EN)

sk2

†

pd(C-AE)

X1 Words in FIFO1

LKB

pd(C-AE)

h(EN)

(X1 + 1) Words in FIFO1

†

sk2

is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than t

sk2

, AEB

may transition high one CLKB cycle later than shown.

NOTE A: FIFO1 write (CSA

= L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been

read from the FIFO.

Figure 11. T iming for AEB When FIFO1 Is Almost Empty

pd(C-AE)

su(EN)

CLKB

AEA

ENA

ENB

h(EN)

su(EN)

sk2

‡

X2 Words in FIFO2

CLKA

pd(C-AE)

h(EN)

(X2 + 1) Words in FIFO2

‡

sk2

is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA

to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

sk2

, AEA

may transition high one CLKA cycle later than shown.

NOTE A: FIFO2 write (CSB

= L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been

read from the FIFO.

Figure 12. Timing for AEA When FIFO2 Is Almost Empty

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pd(C-AF)

su(EN)

CLKA

AFA

ENB

ENA

su(EN)

h(EN)

[512 – (Y1 + 1)] Words in FIFO1

h(EN)

sk2

†

CLKB

(512 – Y1) Words in FIFO1

†

sk2

is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA

to transition high in the next CLKA cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than t

sk2

, AFA

may transition high one CLKB cycle later than shown.

NOTE A: FIFO1 write (CSA

= L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been

read from the FIFO.

Figure 13. Timing for AFA When FIFO1 Is Almost Full

pd(C-AF)

su(EN)

CLKB

AFB

ENA

ENB

su(EN)

h(EN)

[512 – (Y2 + 1)] Words in FIFO2

h(EN)

sk2

‡

CLKA

(512 – Y2) Words in FIFO2

‡

sk2

is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB

to transition high in the next CLKB cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

sk2

, AFB

may transition high one CLKA cycle later than shown.

NOTE A: FIFO2 write (CSB

= L, W/RB= L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been

read from the FIFO.

Figure 14. Timing for AFB When FIFO2 Is Almost Full

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

CSA

W/RA

su(EN)

h(D)

MBA

ENA

A0–A35

h(EN)

su(D)

CLKB

h(EN)

CSB

su(EN)

pd(C-MF)

MBF1

W/RB

MBB

ENB

B0–B35

FIFO1 Output Register

W1 (remains valid in mail1 register after read)

pd(C-MR)

dis

pd(M-DV)

Figure 15. Timing for Mail1 Register and MBF1 Flag

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKB

CSB

W/RA

MBB

ENB

A0–A35

CLKA

CSA

MBF2

W/RB

MBA

ENA

B0–B35

su(EN)

h(D)

h(EN)

su(D)

h(EN)

su(EN)

pd(C-MF)

FIFO2 Output Register

W1 (remains valid in mail2 register after read)

pd(C-MR)

dis

pd(M-DV)

Figure 16. Timing for Mail2 Register and MBF2 Flag

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): PCB package 28°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PQ package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

MIN MAX UNIT

Supply voltage 4.5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current –4 mA

Low-level output current 8 mA

Operating free-air temperature 0 70 °C

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VCC = 4.5 V, IOH = –4 mA 2.4 V

VCC = 4.5 V, IOL = 8 mA 0.5 V

VCC = 5.5 V, VI = VCC or 0 ±5 µA

VCC = 5.5 V, VO = VCC or 0 ±5 µA

VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA

CSA = V

A0–A35 0

CSB = V

B0–B35 0

∆I

‡

VCC = 5.5 V , One input at 3.4 V ,

CSA = V

A0–A35 1

Other in uts at V

GND

CSB = V

B0–B35 1

All other inputs 1

VI = 0, f = 1 MHz 4 pF

VO = 0, f = 1 MHz 8 pF

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 17)

’ACT3632-15 ’ACT3632-20 ’ACT3632-30

MIN MAX MIN MAX MIN MAX

UNIT

clock

Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz

Clock cycle time, CLKA or CLKB 15 20 30 ns

w(CLKH)

Pulse duration, CLKA and CLKB high 6 8 10 ns

w(CLKL)

Pulse duration, CLKA and CLKB low 6 8 10 ns

su(D)

Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑ 4 5 6 ns

su(EN)

Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W

/RB, ENB, and MBB before CLKB↑

4.5 5 6 ns

su(RS)

Setup time, RST1 or RST2 low before CLKA↑ or CLKB↑

5 6 7 ns

su(FS)

Setup time, FS0 and FS1 before RST1 and RST2 high 7.5 8.5 9.5 ns

h(D)

Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑ 1 1 1 ns

h(EN)

Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑

1 1 1 ns

h(RS)

Hold time, RST1 or RST2 low after CLKA↑ or CLKB↑

4 4 5 ns

h(FS)

Hold time, FS0 and FS1 after RST1 and RST2 high 2 3 3 ns

sk1

Skew time between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB

7.5 9 11 ns

sk2

Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA

, and AFB

12 16 20 ns

Requirement to count the clock edge as one of at least four needed to reset a FIFO

Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle.

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

= 30 pF (see Figures 1 through 17)

’ACT3632-15 ’ACT3632-20 ’ACT3632-30

PARAMETER

MIN MAX MIN MAX MIN MAX

UNIT

max

66.7 50 33.4 MHz

Access time, CLKA↑ to A0–A35 and CLKB↑ to B0–B35 3 11 3 13 3 15 ns

pd(C-IR)

Propagation delay time, CLKA↑ to IRA and CLKB↑ to IRB 2 8 2 10 2 12 ns

pd(C-OR)

Propagation delay time, CLKA↑ to ORA and CLKB↑ to ORB 1 8 1 10 1 12 ns

pd(C-AE)

Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB 1 8 1 10 1 12 ns

pd(C-AF)

Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB 1 8 1 10 1 12 ns

pd(C-MF)

Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and CLKB↑ to MBF2

low or MBF1 high

0 8 0 10 0 12 ns

pd(C-MR)

Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to A0–A35

‡

3 13.5 3 15 3 17 ns

pd(M-DV)

Propagation delay time, MBA to A0–A35 valid and MBB to B0–B35 valid

3 11 3 13 3 15 ns

pd(R-F)

Propagation delay time, RST1 low to AEB low, AFA high, and MBF1

high, and RST2 low to AEA low, AFB high, and MBF2 high

1 15 1 20 1 30 ns

Enable time, CSA and W/RA low to A0–A35 active and CSB low and W

/RB high to B0–B35 active

2 12 2 13 2 14 ns

dis

Disable time, CSA or W/RA high to A0–A35 at high impedance and CSB

high or W/RB low to B0–B35 at high impedance

1 8 1 12 1 11 ns

†

Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high

‡

Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

1.5 V1.5 V

3 V

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data,

Enable

Input

1.5 V 1.5 V

3 V

GND

High-Level

Input

Low-Level

Input

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

1.5 V 1.5 V

1.5 V1.5 V

3 V

GND

In-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

From Output

Under Test

30 pF (see Note A)

680 Ω

1.1 kΩ

5 V

LOAD CIRCUIT

PLZ

≈ 3 V

PHZ

1.5 V 1.5 V

3 V

GND

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PZL

1.5 V

≈ 0 V

1.5 V

PZH

Output Enable

Low-Level

Output

High-Level

Output

NOTES: A. Includes probe and jig capacitance

B. t

PZL

and t

PZH

are the same as ten.

C. t

PLZ

and t

PHZ

are the same as t

dis

Figure 17. Load Circuit and Voltage Waveforms

SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

100

150

200

250

300

0 10203040506070

I – Supply Current – mA

CC(f)

SUPPLY CURRENT

CLOCK FREQUENCY

clock

– Clock Frequency – MHz

data

= 1/2 f

clock

TA = 75°C CL = 0 pF

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

Figure 18

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