Texas Instruments SN74ACT2235-20FN, SN74ACT2235-20PAG, SN74ACT2235-20PM, SN74ACT2235-30FN, SN74ACT2235-30FNR Datasheet
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SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
D
Independent Asynchronous Inputs and
Outputs
D
Low-Power Advanced CMOS Technology
D
Bidirectional
D
Dual 1024 by 9 Bits
D
Programmable Almost-Full/Almost-Empty
Flag
D
Empty, Full, and Half-Full Flags
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2235 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates up to 50 MHz, with access times of 25 ns in a bit-parallel format.
The SN74ACT2235 consists of bus-transceiver circuits, two 1024 × 9 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable (GAB
and GBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 2 shows the eight fundamental bus-management functions that can be performed with the
SN74ACT2235.
D
Access Times of 25 ns With a 50-pF Load
D
Data Rates up to 50 MHz
D
Fall-Through Times of 22 ns Maximum
D
High Output Drive for Direct Bus Interface
D
Package Options Include 44-Pin Plastic
Leaded Chip Carriers (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
For more information on this device family, see the application report,
SN74ACT2235
, literature number SCAA010.
The SN74ACT2235 is characterized for operation from 0°C to 70°C.
FN PACKAGE
(TOP VIEW)
GAB
SAB
DBF
GNDB0B1
42 41 4043
UNCKA
EMPTY A
B2
39
B3
38
B4
37
V
36
CC
B5
35
B6
34
B7
33
B8
32
GND
31
AF/AEB
30
HFB
29
FULLB
LDCKB
A3
A4
V
CC
A5
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
A2A1A0
7
8
9
10
11
12
13
14
15
16
17
1819
FULLA
GND
GBA
SBA
54321644
20 21 22 23
UNCKB
EMPTYB
DAF
RSTA
24 25 26 27 28
RSTB
1K × 9 × 2 Asynchronous FIFO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
PAG OR PM PACKAGE
(TOP VIEW)
V
CC
A3
A4
V
CC
GND
GND
A5
A6
V
CC
V
CC
A7
A8
GND
GND
AF/AEA
HFA
CC
V
A1
A0
GND
A2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 25 26 27 28 29 30 31 322423
NC
FULLA
LDCKA
UNCKB
GBA
GND
DAF
RSTA
EMPTYB
SBA
NC
SAB
GAB
RSTB
GND
DBF
EMPTYA
GNDB1B2
B0
NC
UNCKA
FULLB
LDCKB
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
V
CC
B3
B4
GND
GND
V
CC
B5
B6
V
CC
B7
B8
GND
GND
AF/AEB
HFB
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
logic symbol
†
Φ
44
SAB
1
SBA
43
GAB
2
GBA
RSTA
LDCKA
UNCKA
FULLA
EMPTYA
AF/AEA
22
21
DAF
17
26
18
25
15
16
HFA HFB
4
A0
5
A1
6
A2
7
A3
8
A4
10
A5
11
A6
12
A7
13
A8
1
MODE
0
EN1
EN2
Reset A
DEF A FLAG
LDCKA
UNCKA
FULLA
EMPTY A
ALMOST-FULL/
ALMOST-EMPTY A
HALF-FULL A
0
A Data
8
FIFO
1024 × 9 × 2
SN74ACT2235
RESET B
DEF B FLAG
LDCKB
UNCKB
FULL B
EMPTYB
ALMOST-FULL/
ALMOST-EMPTY A
HALF-FULL B
0
B Data
8
23
24
28
19
27
20
30
29
41
40
39
38
37
35
34
33
32
RSTB
DBF
LDCKB
UNCKB
FULLB
EMPTYB
AF/AEB
B0
B1
B2
B3
B4
B5
B6
B7
B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
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3
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
logic diagram (positive logic)
SAB
SBA
Φ
HFB
AF/AEB
EMPTYB
UNCKB
FIFO B
1024 × 9
RSTB
DBF
FULLB
LDCKB
GBA
GAB
RSTA
DAF
FULLA
LDCKA
A0
One of Nine Channels
To Other Channels
Φ
FIFO A
1024 × 9
D
Q
Q
One of Nine Channels
D
B0
HFA
AF/AEA
EMPTYA
UNCKA
To Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
TERMINAL
NAME NO.
AF/AEA
AF/AEB
A0–A8
B0–B8
DAF
DBF
EMPTYA
EMPTYB
FULLA
FULLB
HFA
HFB
LDCKA
LDCKB
GAB
GBA
RSTA
RSTB
SAB
SBA
UNCKA
UNCKB
†
Terminals listed are for the FN package.
†
15
30
4–8,
10–13
32–35,
37–41
21
24
20
25
18
27
16
29
17
28
2
43
22
23
1
44
19
26
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or fewer words
O
or 1024–X words. AF/AEA is low when FIFO A contains between (X + 1) or (1023 – X) words. The operation
of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
I/O A-data inputs and outputs
I/O B-data inputs and outputs
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0–A8 as the
almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF
I
of B0–B8 as the almost-full/almost-empty offset value for FIFO B (Y).
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high when
O
they are not empty.
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they are
O
not full.
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more words and
O
low when they contain 511 or fewer words.
Load clocks. Data on A0–A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on B0–B8 is
written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA and LDCKB have
I
no effect on the data residing in memory .
Output enables. GAB, GBA control the transceiver functions. When GBA is low, A0–A8 are in the
I
high-impedance state. When GAB is low, B0–B8 are in the high-impedance state.
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
I
EMPTYB
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level selects
real-time data and a high level selects stored data. Eight fundamental bus-management functions can be
I
performed as shown in Figure 2.
Unload clocks. Data in FIFO A is read to B0–B8 on a low-to-high transition of UNCKB. Data in FIFO B is read
to A0–A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and UNCKB have no
I
effect on data residing in memory.
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
Terminal Functions
stores the binary value
, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value for FIFO A (X) and for FIFO B (Y) is either a user-defined value or the
default values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB
is programmed in the same manner for FIFO B.
user-defined X
Take DAF
If RSTA
With DAF
To retain the current offset for the next reset, keep DAF
default X
To redefine AF/AE using the default value of X = 256, hold DAF
from high to low. This stores A0–A8 as X.
is not already low, take RSTA low .
held low, take RSTA high. This defines AF/AEA using X.
low.
high during the reset cycle.Figure 1
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5
6
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
RSTA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAF
LDCKA
A0–A8
UNCKA
Q0–Q8
EMPTYA
FULLA
HFA
Invalid
Word1Word
2
Word
257
Word
512
Word 1
Word
768
Don’t Care
Word
1024
Word
2
Word
257
Word
258
Word
513
Don’t Care
Word
514
Word
768
Word
769
Word
1024
Word
1024
X
‡
Invalid
AF/AEA
Set Flag to Empty + 256/
Empty + 256
Full – 256 EmptyFull – 256 Half Full Empty + 256
Full – 256 (default)
†
Operation of FIFO B is identical to that of FIFO A.
‡
Last valid data stays on outputs when FIFO goes empty due to a read.
Figure 1. Timing Diagram for FIFO A
FullHalf Full
Set Flag to
Empty + X/Full – X
Load X into
Flag Register
≤≤
(0 X 511)
†
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
Bus A
Bus A
FIFO A
In
Out In
SABLSBAXGABHGBA
SABXSBALGABLGBA
In
Out
FIFO B
FIFO A
In
Out In
FIFO A
Out
FIFO B
Out
L
H
Bus B
Bus B
Bus A
Bus A
FIFO A
In Out
FIFO B
Out In
SABXSBAXGABLGBA
L
FIFO A
In Out
FIFO B
Out In
SABHSBALGABHGBA
H
FIFO A
In
Out
Bus B
Bus B
Bus A
Bus A
FIFO B
Out In
SABHSBAXGABHGBA
L
FIFO A
In
Out In
SABXSBAHGABLGBA
Out
FIFO B
H
Figure 2. Bus-Management Functions
Bus B
Bus B
Bus A
Bus A
FIFO B
Out In
SABLSBAHGABHGBA
H
FIFO A
In
Out In
SABHSBAHGABHGBA
Out
FIFO B
H
Bus B
Bus B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ACT2235
UNIT
IOHHigh-level output current
mA
IOLLow-level output current
mA
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
SELECT-MODE CONTROL
CONTROL
SAB SBA A BUS B BUS
L L Real-time B to A bus Real-time A to B bus
L H FIFO B to A bus Real-time A to B bus
H L Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus
OUTPUT-ENABLE CONTROL
CONTROL
GAB GBA A BUS B BUS
H H A bus enabled B bus enabled
L H A bus enabled Isolation/input to B bus
H L Isolation/input to A bus B bus enabled
L L Isolation/input to A bus Isolation/input to B bus
Figure 2. Bus-Management Functions (Continued)
OPERATION
OPERATION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
CC
: Control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 1): FN package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
PAG package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PM package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Maximum junction temperature, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
stg
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
ACT2235-20 ACT2235-30 ACT2235-40 ACT2235-60
MIN MAX MIN MAX MIN MAX MIN MAX
V
V
V
T
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 2 2 V
IH
Low-level input voltage 0.8 0.8 0.8 0.8 V
IL
p
p
Operating free-air temperature 0 70 0 70 0 70 0 70 °C
A
A or B ports –8 –8 –8 –8
Status flags –8 –8 –8 –8
A or B ports 16 16 16 16
Status flags 8 8 8 8
†
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
UNIT
f
Clock frequenc
MH
twPulse duration
ns
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
OH
Flags VCC = 4.5 V, IOL = 8 mA 0.5
OL
I/O ports VCC = 4.5 V, IOL = 16 mA 0.5
I
I
I
OZ
‡
I
CC
§
∆I
CC
C
i
C
o
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
ICC is tested with outputs open.
§
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 3)
clock
t
su
t
h
Setup time
Hold time
VCC = 4.5 V, IOH = –8 mA 2.4 V
VCC = 5.5 V, VI = VCC or 0 ±5 µA
VCC = 5.5 V, VO = VCC or 0 ±5 µA
VI = VCC – 0.2 V or 0 10 400 µA
VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 1 mA
VI = 0, f = 1 MHz 4 pF
VO = 0, f = 1 MHz 8 pF
’ACT2235-20 ’ACT2235-30 ’ACT2235-40 ’ACT2235-60
MIN MAX MIN MAX MIN MAX MIN MAX
LDCKA or LDCKB 50 33 25 16.7
y
UNCKA or UNCKB
RSTA or RSTB low 20 20 25 25
LDCKA or LDCKB low 8 10 14 20
LDCKA or LDCKB high 8 10 14 20
UNCKA or UNCKB low 8 10 14 20
UNCKA or UNCKB high 8 10 14 20
DAF or DBF high 10 10 10 10
Data before LDCKA
or LDCKB↑
Define AF/AE:
D0–D8 before DAF
Define AF/AE: DAF
before RSTA
Define AF/AE (default):
DAF
or DBF high before
RSTA
or RSTB↑
RSTA or RSTB inactive (high)
before LDCKA or LDCKB↑
Data after LDCKA or LDCKB↑ 1 1 2 2
Define AF/AE: D0–D8
after DAF
Define AF/AE: DAF
after RSTA
Define AF/AE (default):
DAF
RSTA
or DBF↓
or DBF high after
or RSTB↑
or DBF↓
or DBF↓
or RSTB↑
or DBF low
or RSTB↑
50 33 25 16.7
4 4 5 5
5 5 5 5
7 7 7 7
5 5 5 5
5 5 5 5
0 0 0 0
0 0 0 0
0 0 0 0
ns
ns
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74ACT2235
PARAMETER
UNIT
f
MH
t
B or A
ns
EMPTYB
↓
PHL
,
B or A
,
CpdPower dissipation capacitance per 1K bits
C
50 pF
pF
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
max
pd
t
PLH
t
PHL
t
PLH
t
t
pd
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
= 50 pF (unless otherwise noted) (see Figure 3)
L
FROM TO
(INPUT) (OUTPUT)
LDCK 50 33 25 16.7
UNCK 50 33 25 16.7
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
RSTA↓, RSTB↓
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
RSTA↓, RSTB
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
RSTA↓, RSTB↓
SAB or SBA
A or B
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
GBA or GAB A or B 2 11 2 11 2 13 2 15 ns
GBA or GAB A or B 1 9 1 9 1 11 1 13 ns
EMPTYA,
EMPTYB
EMPTYA,
FULLA, FULLB 4 15 4 15 4 17 4 19
FULLA, FULLB
FULLA, FULLB 2 15 2 15 2 17 2 19
AF/AEA,
AF/AEB
HFA, HFB 2 15 2 15 2 17 2 19
HFA, HFB
‡
AF/AEA,
AF/AEB
’ACT2235-20 ’ACT2235-30 ’ACT2235-40 ’ACT2235-60
MIN TYP†MAX MIN MAX MIN MAX MIN MAX
8 22 8 22 8 24 8 26
12 17 25 12 25 12 35 12 45
4 15 4 15 4 17 4 19 ns
2 17 2 17 2 19 2 21
2 18 2 18 2 20 2 22
4 15 4 15 4 17 4 19
2 15 2 15 2 17 2 19
4 18 4 18 4 20 4 22
1 15 1 15 1 17 1 19
1 11 1 11 1 12 1 14
1 11 1 11 1 12 1 14
2 18 2 18 2 20 2 22
2 18 2 18 2 20 2 22
z
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
p
10
PARAMETER TEST CONDITIONS TYP UNIT
p
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Outputs enabled
Outputs disabled
p
,f = 5 MHz
=
L
71
57
p
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7 V
From Output
Under Test
Timing
Input
Data
Input
Input
t
PLH
Output
S1
CL = 50 pF
(see Note A)
LOAD CIRCUIT
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
500 Ω
1.5 V
t
h
500 Ω
Test
Point
t
PHL
3 V
0 V
3 V
0 V
3 V
0 V
V
V
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 7 V
Output
Waveform 2
S1 at Open
PARAMETER S1
t
t
t
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PZH
en
t
PZL
t
PHZ
dis
t
PLZ
t
PLH
pd
t
PHL
PULSE DURATION
t
1.5 V
t
1.5 V
PLZ
PHZ
t
w
Open
Closed
Open
Closed
Open
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
≈ 3.5 V
V
OL
V
OH
≈ 0 V
NOTE A: CL includes probe and jig capacitance.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
typ + 8
typ + 6
typ + 4
typ + 2
pd
t – Propagation Delay Time – ns
typ – 2
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
VCC = 5 V
TA = 25°C
RL = 500 Ω
typ
0 50 100 200 250150 300
CL – Load Capacitance – pF
Figure 4
POWER-DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
typ + 2
VCC = 5 V
fi = 5 MHz
typ + 1
typ – 1
– Power Dissipation Capacitance – pF
typ – 2
pd
C
typ – 3
TA = 25°C
typ
4.5 4.6 4.7 4.9 54.8 5.1 5.2 5.3 5.4 5.5
VCC – Supply Voltage – V
Figure 5
12
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