Texas Instruments SN74ACT2227DW, SN74ACT2227DWR, SN74ACT2229DW, SN74ACT2229DWR Datasheet
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each – SN74ACT2227
256 Words by 1 Bit Each – SN74ACT2229
D
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident on Each
FIFO
D
Input-Ready Flags Synchronized to Write
Clocks
D
Output-Ready Flags Synchronized to Read
Clocks
D
Half-Full and Almost-Full/Almost-Empty
Flags
D
Support Clock Frequencies up to 60 MHz
D
Access Times of 9 ns
D
3-State Data Outputs
D
Low-Power Advanced CMOS Technology
D
Packaged in 28-Pin SOIC Package
description
The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering
applications including elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip
is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for
independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),
half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when
the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the
high-impedance state when its output-enable (1OE or 2OE) input is low.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or
2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock
(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits
are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data
output is not stored in the FIFO.
The SN74ACT2227 and SN74ACT2229 are characterized for operation from –40°C to 85°C.
For more information on this device family, see the application report
FIFOs With a Word Width of One Bit
(literature number SCAA006).
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1HF
1AF/AE
1WRTCLK
1WRTEN
1IR
1D
GND
GND
1RESET
2Q
2OR
2RDEN
2RDCLK
2OE
1OE
1RDCLK
1RDEN
1OR
1Q
2RESET
V
CC
V
CC
2D
2IR
2WRTEN
2WRTCLK
2AF/AE
2HF
DW PACKAGE
(TOP VIEW)
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols
†
RESET
9
6
1D
1Q
24
Φ
FIFO 64 × 1
SN74ACT2227
3
1WRTCLK
WRTEN
4
1WRTEN
WRTCLK
27
1RDCLK
RDCLK
EN1
28
1OE
1IR
5
IN RDY
1HF
1
HALF FULL
1AF/AE
2
ALMOST FULL/EMPTY
1OR
25
OUT RDY
1RESET
1
RDEN
26
1RDEN
RESET
23
20
2D
2Q
10
17
2WRTCLK
WRTEN
18
2WRTEN
13
2RDCLK
EN2
14
2OE
2IR
19
2HF
15
2AF/AE
16
2OR
11
RDEN
12
2RDEN
2RESET
RESET
9
6
1D
1Q
24
Φ
FIFO 256 × 1
SN74ACT2229
3
1WRTCLK
WRTEN
4
1WRTEN
WRTCLK
27
1RDCLK
RDCLK
EN1
28
1OE
1IR
5
IN RDY
1HF
1
HALF FULL
1AF/AE
2
ALMOST FULL/EMPTY
1OR
25
OUT RDY
1RESET
1
RDEN
26
1RDEN
RESET
23
20
2D
2Q
10
17
2WRTCLK
WRTEN
18
2WRTEN
13
2RDCLK
EN2
14
2OE
2IR
19
2HF
15
2AF/AE
16
2OR
11
RDEN
12
2RDEN
2RESET
WRTCLK
RDCLK
WRTCLK
RDCLK
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
2
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
2
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227 functional block diagram (each FIFO)
Synchronous
Read Control
Read
Pointer
Location 1
Location 2
Dual-Port
SRAM
64 × 1
Location 63
Location 64
Synchronous
Write Control
Write
Pointer
Status
Register
D
RDCLK
RDEN
WRTCLK
WRTEN
RESET
Q
AF/AE
HF
IR
OR
Reset Logic
OE
SN74ACT2229 functional block diagram (each FIFO)
Synchronous
Read Control
Read
Pointer
Location 1
Location 2
Dual-Port
SRAM
256 × 1
Location 255
Location 256
Synchronous
Write Control
Write
Pointer
Status
Register
D
RDCLK
RDEN
WRTCLK
WRTEN
RESET
Q
AF/AE
HF
IR
OR
Reset Logic
OE
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
1AF/AE
2AF/AE
2
16
O
Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or fewer from a full or empty
state. AF/AE is set high after reset.
1D
2D
6
20
I Data input
GND 7, 8 Ground
1HF
2HF
1
15
O
Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FIFO depth.
HF is set low after reset.
1IR
2IR
5
19
O
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low , the FIFO is full
and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of
WRTCLK after reset.
1OE
2OE
28
14
I
Output enable. The data output of a FIFO is active when OE is high and in the high-impedance state when OE
is low.
1OR
2OR
25
11
O
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is
empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during
reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
1Q
2Q
24
10
O
Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
OR for the FIFO is asserted high to indicate ready data.
1RDCLK
2RDCLK
27
13
I
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is
synchronous with the low-to-high transition of RDCLK.
1RDEN
2RDEN
26
12
I
Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high
transition of RDCLK.
1RESET
2RESET
9
23
I
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK
must occur while RESET
is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must
be reset after power up.
V
CC
21, 22 Supply voltage
1WRTCLK
2WRTCLK
3
17
I
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with
the low-to-high transition of WRTCLK.
1WRTEN
2WRTEN
4
18
I Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK.
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