Texas Instruments SN74ACT2228DW, SN74ACT2228DWR, SN74ACT2226DW Datasheet
SN74ACT2226, SN74ACT2228
DUAL 64 × 1, DUAL 256 × 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
D
Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each – SN74ACT2226
256 Words by 1 Bit Each – SN74ACT2228
D
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident on Each
FIFO
D
Input-Ready Flags Synchronized to Write
Clocks
D
Output-Ready Flags Synchronized to Read
Clocks
D
Half-Full and Almost-Full/Almost-Empty
Flags
D
Support Clock Frequencies up to 22 MHz
D
Access Times of 20 ns
D
Low-Power Advanced CMOS Technology
D
Packaged in 24-Pin Small-Outline
1AF/AE
1WRTCLK
1WRTEN
1RESET
2RDEN
2RDCLK
DW PACKAGE
1HF
1IR
1D
GND
2Q
2OR
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
1RDCLK
1RDEN
1OR
1Q
2RESET
V
CC
2D
2IR
2WRTEN
2WRTCLK
2AF/AE
2HF
Integrated-Circuit Package
description
The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering
applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip
is arranged as 64 ×1 (SN74ACT2226) or 256 ×1 (SN74ACT2228) and has control signals and status flags for
independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),
half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when
the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or
2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock
(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits
are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data
output is not stored in the FIFO.
The SN74ACT2226 and SN74ACT2228 are characterized for operation from –40°C to 85°C.
For more information on this device family, see the application report
FIFOs With a Word Width of One Bit
(literature number SCAA006).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN74ACT2226, SN74ACT2228
DUAL 64 × 1, DUAL 256 × 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
logic symbols
†
1RESET
1WRTCLK
1WRTEN
1RDCLK
1RDEN
2RESET
2WRTCLK
2WRTEN
2RDCLK
2RDEN
1D
2D
8
3
4
24
23
6
20
15
16
12
11
18
RESET
WRTCLK
WRTEN
RDCLK
RDEN
RESET
WRTCLK
WRTEN
RDCLK
RDEN
Φ
FIFO 64 × 1
SN74ACT2226
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
22
21
17
13
14
10
5
1
2
9
1IR
1HF
1AF/AE
1OR
1Q
2IR
2HF
2AF/AE
2OR
2Q
Φ
FIFO 256 × 1
SN74ACT2228
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
1D
2D
8
3
4
24
23
6
20
15
16
12
11
18
1RESET
1WRTCLK
1WRTEN
1RDCLK
1RDEN
2RESET
2WRTCLK
2WRTEN
2RDCLK
2RDEN
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
RESET
WRTCLK
WRTEN
RDCLK
RDEN
RESET
WRTCLK
WRTEN
RDCLK
RDEN
22
21
17
13
14
10
5
1
2
9
1IR
1HF
1AF/AE
1OR
1Q
2IR
2HF
2AF/AE
2OR
2Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SN74ACT2226 functional block diagram (each FIFO)
D
RDCLK
RDEN
WRTCLK
WRTEN
Synchronous
Read Control
Synchronous
Write Control
Read
Pointer
Write
Pointer
SN74ACT2226, SN74ACT2228
DUAL 64 × 1, DUAL 256 × 1
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
Location 1
Location 2
Dual-Port
SRAM
64 × 1
Location 63
Location 64
Status
Reset
RESET
Logic
SN74ACT2228 functional block diagram (each FIFO)
D
RDCLK
RDEN
WRTCLK
WRTEN
RESET
Synchronous
Read Control
Synchronous
Write Control
Reset
Logic
Read
Pointer
Write
Pointer
Status
Register
Location 1
Location 2
Dual-Port
SRAM
256 × 1
Location 255
Location 256
Register
Q
AF/AE
HF
IR
OR
Q
AF/AE
HF
IR
OR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ACT2226, SN74ACT2228
I/O
DESCRIPTION
DUAL 64 × 1, DUAL 256 × 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
Terminal Functions
TERMINAL
NAME NO.
1AF/AE
2AF/AE
1D
2D
GND 7 Ground
1HF
2HF
1IR
2IR
1OR
2OR
1Q
2Q
1RDCLK
2RDCLK
1RDEN
2RDEN
1RESET
2RESET
V
CC
1WRTCLK
2WRTCLK315
1WRTEN
2WRTEN
2
14
6
18
1
13
5
17
22
10
21
9
24
12
23
11
8
20
19 Supply voltage
4
16
Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or less from a full or empty
O
state. AF/AE is set high after reset.
I Data input
Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FIFO
O
depth. HF is set low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low , the FIFO is full
and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of
O
WRTCLK after reset.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is
empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during
O
reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
O
OR for the FIFO is asserted high to indicate ready data.
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is
I
synchronous with the low-to-high transition of RDCLK.
Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high
I
transition of RDCLK.
Reset. T o reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WR TCLK
must occur while RESET
I
be reset after power up.
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous
I
with the low-to-high transition of WRTCLK.
Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of
I
WRTCLK.
is low. This sets HF , IR, and OR low and AF/AE high. Before it is used, a FIFO must
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...