Datasheet SN74AC574DBLE, SN74AC574DBR, SN74AC574DW, SN74AC574DWR, SN74AC574N Datasheet (Texas Instruments)

SN54AC574, SN74AC574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS541B – OCTOBER 1995 – REVISED JUNE 1996

D

3-State Outputs Drive Bus Lines Directly

D

EPIC

t

(Enhanced-Performance Implanted

CMOS) 1-µm Process

D

Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIP Packages

description

These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight flip-flops of the ′AC574 are D-type
edge-triggered flip-flops. On the positive transi­tion of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high­impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.

) input can be used

SN54AC574 ...J OR W PACKAGE

SN74AC574 . . . DB, DW, N, OR PW PACKAGE

SN54AC574 . . . FK PACKAGE

3D
4D
5D
6D
7D

(TOP VIEW)

1

OE

2

1D

3

2D

4

3D

5

4D

6

5D

7

6D

8

7D

9

8D

GND

10

(TOP VIEW)

2D1DOE

3 2 1 20 19

4
5
6
7
8

910111213

8D

GND

20
19
18
17
16
15
14
13
12
11

CLK

V

8Q

CC

V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK

1Q

18
17
16
15
14

7Q

CC

2Q
3Q
4Q
5Q
6Q

OE

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
The SN54AC574 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74AC574 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each flip-flop)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

INPUTS

OE CLK D

L ↑ H H
L ↑ LL
L H or L X Q

H X X Z

OUTPUT

Q

0

Copyright  1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCAS541B – OCTOBER 1995 – REVISED JUNE 1996

logic symbol

OE

CLK

1D
2D
3D
4D
5D
6D
7D
8D

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

†

1
11

2
3
4
5
6
7
8
9

EN

1D

C1

19
18
17
16
15
14
13
12

logic diagram (positive logic)

1

OE

11

CLK

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q

1D

2

To Seven Other Channels

1D

C1

19

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V
Input clamp current, IIK (VI < 0 or VI > V
Output clamp current, IOK (VO < 0 or VO > V

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at T

Storage temperature range, T

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

= 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . .

A

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC)

DW package 1.6 W. . . . . . . . . . . . . . . . .

N package 1.3 W. . . . . . . . . . . . . . . . . . .

PW package 0.7 W. . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

1Q

‡

‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.

2

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UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

I

mA

V

V

I

mA

SN54AC574, SN74AC574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS541B – OCTOBER 1995 – REVISED JUNE 1996

recommended operating conditions (see Note 3)

SN54AC574 SN74AC574

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

V

O

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 2 6 2 6 V

VCC = 3 V 2.1 2.1

High-level input voltage

Low-level input voltage

Input voltage 0 V
Output voltage 0 V

High-level output current

Low-level output current

Operating free-air temperature –55 125 –40 85 °C

VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5V
VCC = 5.5 V 1.65 1.65

VCC = 3 V –12 –12
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24

3.15 3.15

1.35 1.35

CC
CC

–24 –24

24 24

0 V
0 V

CC
CC

V

V

V
V

mA

mA

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54AC574 SN74AC574

MIN TYP MAX MIN MAX MIN MAX

I
I
I
C

OH

OL

I
OZ
CC

i

CC

3 V 2.9 2.9 2.9

IOH = –50 µA

IOH = –12 mA 3 V 2.56 2.4 2.46

= –24

OH

IOL = 50 µA

IOL = 12 mA 3 V 0.36 0.5 0.44

= 24

OL

VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±2.5 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
VI = VCC or GND 5 V 4.5 pF

4.5 V 4.4 4.4 4.4

5.5 V 5.4 5.4 5.4

4.5 V 3.94 3.7 3.76

5.5 V 4.94 4.7 4.76
3 V 0.1 0.1 0.1

4.5 V 0.1 0.1 0.1

5.5 V 0.1 0.1 0.1

4.5 V 0.36 0.5 0.44

5.5 V 0.36 0.5 0.44

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3

SN54AC574, SN74AC574

UNIT

UNIT

PARAMETER

UNIT

CLK

Q

ns

OE

Q

ns

OE

Q

ns

PARAMETER

UNIT

CLK

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCAS541B – OCTOBER 1995 – REVISED JUNE 1996

timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)

TA = 25°C SN54AC574 SN74AC574
MIN MAX MIN MAX MIN MAX

t
t
t

timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)

t
t
t

switching characteristics over recommended operating free-air temperature range,
V

CC

Pulse duration, CLK high or low 6 7.5 7 ns

w

Setup time, data before CLK↑ 2.5 6.5 3 ns

su

Hold time, data after CLK↑ 1.5 2.5 1.5 ns

h

TA = 25°C SN54AC574 SN74AC574
MIN MAX MIN MAX MIN MAX

Pulse duration, CLK high or low 4 5 5 ns

w

Setup time, data before CLK↑ 1.5 3.5 2 ns

su

Hold time, data after CLK↑ 1.5 2.5 1.5 ns

h

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

TA = 25°C SN54AC574 SN74AC574

MIN TYP MAX MIN MAX MIN MAX

75 112 55 60 MHz

3.5 8.5 13.5 1 16.5 3.5 15

3.5 7.5 12 1 15 3.5 13.5

2.5 7 11 1 13 2.5 12
3 6.5 10.5 1 12.5 3 11.5

3.5 7.5 12 1 14 2.5 13
2 5.5 9 1 10.5 1.5 10

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

TO TO

(INPUT) (OUTPUT)

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

TA = 25°C SN54AC574 SN74AC574

MIN TYP MAX MIN MAX MIN MAX

95 153 85 85 MHz

2 6 9.5 1.5 11.5 2 11
2 5.5 8.5 1.5 10.5 2 9.5
2 5 8.5 1.5 9.5 2 9
2 5 8 1.5 9.5 1.5 9
2 6 9.5 1.5 11.5 1.5 10.5
1 4.5 7.5 1.5 9 1 8.5

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

TO TO

(INPUT) (OUTPUT)

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

pd

4

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From Output
Under Test

CL = 50 pF

(see Note A)

Input

50% V

500 Ω

LOAD CIRCUIT

t

w

CC

VOLTAGE WAVEFORMS

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCAS541B – OCTOBER 1995 – REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

2 × V

500 Ω

S1

50% V

CC

3 V

0 V

CC

Open

Timing Input

Data Input

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

50% V

VOLTAGE WAVEFORMS

SN54AC574, SN74AC574

WITH 3-STATE OUTPUTS

Open

2 × V

CC

Open

V

0 V

V

0 V

CC

CC

50% V

CC

CC

t

50% V

h

CC

Input

t

PLH

In-Phase

Output

t

PHL

Out-of-Phase

Output

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.

50% V

CC

50% V

50% V

VOLTAGE WAVEFORMS

50% V

CC

CC

Figure 1. Load Circuit and Voltage Waveforms

CC

t

PHL

50% V

t

PLH

50% V

CC

CC

V

0 V

V

V

V

V

CC

OH

OL

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

CC

t

PZL

t

PZH

CC

CC

50% V

VOL + 0.3 V

VOH – 0.3 V

50% V

CC

t

PLZ

50% V

t

PHZ

50% V

VOLTAGE WAVEFORMS

CC

V

0 V

[

V

V

[

CC

V

OL

OH

0 V

CC

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5

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