Texas Instruments SN74AC373DBLE, SN74AC373DBR, SN74AC373DW, SN74AC373DWR, SN74AC373N Datasheet
...
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
D
3-State Noninverting Outputs Drive Bus
Lines Directly
D
Full Parallel Access for Loading
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB) and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
SN54AC373 ...J OR W PACKAGE
SN74AC373 . . . DB, DW, N, OR PW PACKAGE
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
CC
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE
) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-
SN54AC373 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1D1QOE
3 2 1 20 19
4
5
6
7
8
910111213
LE
4Q
V
5Q
CC
8Q
18
17
16
15
14
5D
GND
8D
7D
7Q
6Q
6D
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly . The
high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems
without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
1
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
logic symbol
1
OE
11
LE
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
EN
C1
1D
2
5
6
9
12
15
16
19
logic diagram (positive logic)
1
OE
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1D
3
To Seven Other Channels
C1
1D
2
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0 or VO > V
Continuous output current, IO (VO = 0 to VCC)
Continuous current through VCC or GND
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > V
IK
CC)
CC)
DW package 1.6 W. . . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
"
"
"
"
20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
I
mA
V
V
I
mA
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
recommended operating conditions (see Note 3)
SN54AC373 SN74AC373
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
High-level input voltage
Low-level input voltage
Input voltage 0 V
Output voltage 0 V
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5V
VCC = 5.5 V 1.65 1.65
VCC = 3 V –12 –12
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24
3.15 3.15
1.35 1.35
CC
CC
–24 –24
24 24
0 V
0 V
CC
CC
V
V
V
V
mA
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54AC373 SN74AC373
MIN TYP MAX MIN MAX MIN MAX
I
I
I
C
OH
OL
I
OZ
CC
i
CC
3 V 2.9 2.9 2.9
IOH = –50 µA
IOH = –12 mA 3 V 2.56 2.4 2.46
= –24
OH
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.5 0.44
= 24
OL
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.25 ± 5 ± 2.5 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
VI = VCC or GND 5 V 4.5 pF
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AC373, SN74AC373
UNIT
UNIT
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC373 SN74AC373
MIN MAX MIN MAX MIN MAX
t
t
t
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
t
t
t
switching characteristics over recommended operating free-air temperature range,
V
CC
Pulse duration, LE high 5.5 6.5 6 ns
w
Setup time, data before LE↓ 5.5 6.5 6 ns
su
Hold time, data after LE↓ 1 1 1 ns
h
TA = 25°C SN54AC373 SN74AC373
MIN MAX MIN MAX MIN MAX
Pulse duration, LE high 4 5 4.5 ns
w
Setup time, data before LE↓ 4 5 4.5 ns
su
Hold time, data after LE↓ 1 1 1 ns
h
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC373 SN74AC373
MIN TYP MAX MIN MAX MIN MAX
1.5 10 13.5 1 16.5 1.5 15
1.5 9.5 13.0 1 16 1.5 14.5
1.5 10 13.5 1 16.5 1.5 15
1.5 9.5 12.5 1 15 1.5 14
1.5 9 11.5 1 14 1 13
1.5 8.5 11.5 1 13.5 1 13
1.5 10 12.5 1 16 1 14.5
1.5 8 11.5 1 13 1 12.5
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
TO TO
(INPUT) (OUTPUT)
switching characteristics over recommended operating free-air temperature range,
V
operating characteristics, VCC = 5 V, TA = 25°C
4
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TO TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA = 25°C SN54AC373 SN74AC373
MIN TYP MAX MIN MAX MIN MAX
1.5 7 9.5 1 11.5 1.5 10.5
1.5 7 9.5 1 11.5 1.5 10.5
1.5 7.5 9.5 1 12 1.5 10.5
1.5 7 9.5 1 11 1.5 10.5
1.5 7 8.5 1 10.5 1 9.5
1.5 6.5 8.5 1 10 1 9.5
1.5 8 11 1 13.5 1 12.5
1.5 6.5 8.5 1 10.5 1 10
From Output
Under Test
CL = 50 pF
(see Note A)
Input
50% V
500 Ω
LOAD CIRCUIT
t
w
CC
VOLTAGE WAVEFORMS
OCTAL D-TYPE TRANSPARENT LATCHES
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
500 Ω
S1
50% V
CC
3 V
0 V
CC
Open
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
50% V
VOLTAGE WAVEFORMS
SN54AC373, SN74AC373
WITH 3-STATE OUTPUTS
Open
2 × V
CC
Open
V
0 V
V
0 V
CC
CC
50% V
CC
CC
50% V
t
h
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
CC
t
PZL
t
PZH
CC
CC
50% V
VOL + 0.3 V
VOH – 0.3 V
50% V
CC
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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Copyright 1998, Texas Instruments Incorporated
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