Texas Instruments SN74AC373DBLE, SN74AC373DBR, SN74AC373DW, SN74AC373DWR, SN74AC373N Datasheet
...
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
D
3-State Noninverting Outputs Drive Bus
Lines Directly
D
Full Parallel Access for Loading
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB) and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
SN54AC373 ...J OR W PACKAGE
SN74AC373 . . . DB, DW, N, OR PW PACKAGE
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
CC
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE
) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-
SN54AC373 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1D1QOE
3 2 1 20 19
4
5
6
7
8
910111213
LE
4Q
V
5Q
CC
8Q
18
17
16
15
14
5D
GND
8D
7D
7Q
6Q
6D
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly . The
high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems
without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
1
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
logic symbol
1
OE
11
LE
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
EN
C1
1D
2
5
6
9
12
15
16
19
logic diagram (positive logic)
1
OE
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1D
3
To Seven Other Channels
C1
1D
2
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0 or VO > V
Continuous output current, IO (VO = 0 to VCC)
Continuous current through VCC or GND
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > V
IK
CC)
CC)
DW package 1.6 W. . . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
"
"
"
"
20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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