Datasheet SN74ABTR2245DBLE, SN74ABTR2245DBR, SN74ABTR2245DGVR, SN74ABTR2245DW, SN74ABTR2245DWR Datasheet (Texas Instruments)
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SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Outputs Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
High-Impedance State During Power Up
and Power Down
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
T ypical V
OLP
(Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), and Plastic (N)
and Ceramic (J) DIPs
description
These octal transceivers and line drivers are
designed for asynchronous communication
between data buses. The devices transmit data
from the A bus to the B bus or from the B bus to
the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE
) input can be used to disable the device so
the buses are effectively isolated.
Both the A-port and B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
When V
CC
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTR2245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTR2245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
SN54ABTR2245 ...J PACKAGE
SN74ABTR2245 . . . DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
3212019
9
10 11 12 13
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
A2A1DIR
B7
B6 OE
A8
GND
B8
V
CC
SN54ABTR2245 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
B2
17
B3
16
B4
15
A5
6
A6
7
A7
8
A8
9
A2
3
A3
4
A4
5
OE
A1
2
G3
19
3 EN2 [AB]
B5
14
B6
13
B7
12
B8
11
B1
18
3 EN1 [BA]
1
DIR
1
2
logic diagram (positive logic)
DIR
OE
A1
B1
To Seven Other Channels
1
2
19
18
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
output schematic
Output
V
CC
GND
25 Ω
All resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABTR2245 SN74ABTR2245
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –12 –12 mA
I
OL
Low-level output current 12 12 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABTR2245 SN74ABTR2245
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 3.35 3.3 3.35
VCC = 5 V, IOH = –1 mA 3.85 3.8 3.85
V
OH
IOH = –3 mA 3 3.1
V
V
CC
=
4.5 V
IOH = –12 mA 2.6 2.6
IOL = 8 mA 0.65 0.8 0.65
VOLV
CC
= 4.5
V
IOL = 12 mA 0.8 0.8
V
V
hys
100 mV
Control
inputs
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1
I
I
A or B ports
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
±20 ±20 ±20
µ
A
I
OZH
‡
VCC = 2.1 V to 5.5 V, VO = 2.7 V,
OE
≥ 2 V
10 10 10 µA
I
OZL
‡
VCC = 2.1 V to 5.5 V, VO = 0.5 V,
OE
≥ 2 V
–10 –10 –10 µA
I
OZPU
§
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V,
OE
= X
±50 ±50 ±50 µA
I
OZPD
§
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V,
OE
= X
±50 ±50 ±50 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high 50 50 50 µA
I
O
¶
VCC = 5.5 V, VO = 2.5 V –25 –100 –25 –100 –25 –100 mA
=
Outputs high 1 250 250 250 µA
I
CC
A or B ports
V
CC
= 5.5 V,
IO = 0,
Outputs low 24 32 32 32 mA
VI = VCC or GND
Outputs disabled 0.5 250 250 250 µA
p
VCC = 5.5 V,
One input at 3.4 V ,
Outputs enabled 1.5 1.5 1.5
∆I
CC
#
Data inputs
,
Other inputs at
VCC or GND
Outputs disabled 0.05 0.05 0.05
mA
Control
inputs
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1.5 1.5 1.5
C
i
VI = 2.5 V or 0.5 V 3 pF
C
io
VO = 2.5 V or 0.5 V 6 pF
* On products compliant to MIL-PRF–38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
OZH
and I
OZL
include the input leakage current.
§
This parameter is characterized but not production tested.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABTR2245 SN74ABTR2245
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
t
PLH
1 2.5 3.4 1 4 1 3.8
t
PHL
A or B
B or A
1 3.2 4.2 1 4.6 1 4.5
ns
t
PZH
1.5 3.6 4.9 1.5 6.3 1.5 6.1
t
PZL
OE
A or B
1.5 3.9 5.3 1.5 6.6 1.5 6.3
ns
t
PHZ
1.5 3.6 4.7 1.5 5.5 1.5 5.3
t
PLZ
OE
A or B
1.5 3.3 4.4 1.5 4.9 1.5 4.8
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTR2245, SN74ABTR2245
OCTAL TRANSCEIVERS AND LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS680A – MARCH 1997 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1998, Texas Instruments Incorporated
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