Texas Instruments SN74ABTH32543PZ Datasheet

SN54ABTH32543, SN74ABTH32543

36-BIT REGISTERED BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS230F – JUNE 1992 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus+

 Family

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Released as DSCC SMD 5962-9557801NXD

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14 × 14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package

†

767778798081828384858687888990919293949596979899100

494847464544434241403938373635343332313029282726

’ABTH32543 ...PZ PACKAGE

(TOP VIEW)

1A9

1A10

GND

1A1 1
1A12
1A13
1A14

GND
1A15
1A16
1A17
1A18

V

CC

2A1
2A2
2A3
2A4

GND

2A5
2A6
2A7
2A8

GND

2A9

2A10

1B9
1B10
GND
1B11
1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18
V

CC

2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
GND
2B9
2B10

1A8

1A7

1A6

V

CC

GND

2A14

2A11

2A12

2A13

1A5

1A4

1A3

1A2

1A1

1CEBA

1OEBA

1LEBA

1LEAB

1OEAB

1CEAB

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

GND

2A18

2A15

2A16

2A17

2LEAB

2OEAB

2CEBA

2OEBA

2B16

2B15

2CEAB

2B18

2B17

GND

2B13

2B14

2B12

2B11

V

CC

50

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2LEBA

†

The HS package is not production released.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS230F – JUNE 1992 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GND

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

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36

35

34

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32

31

1B7
1B8

1B10
1B11

1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18

2B1

2B4
GND
2B5
2B6
2B7
2B8

1A6
1A8

1A9

1A10
1A11

1A12
1A13
1A14

1A15
1A16

1A18

2A1
2A2
2A3
2A4

GND

2A5
2A7

2A8

GND

1A5

1A3

1A2

1A1

1B2

1B3

1B4

1B5

GND

GND

2A14

2A15

2A16

2A17

2A18

2CEBA

2B18

2B17

2B16

2B14

GND

2B15

1A7

1CEAB

1B9

2B3

GND

2A6

2A9
2A10
2A11
2A12

GND
2B9

2B10
2B11

2B12

1B1

1A4

SN54ABTH32543 . . . HS PACKAGE

†

(TOP VIEW)

1A17

V

CC

2OEBA

2LEBA

CC

V

2LEAB

2OEAB

2CEAB

2B2

V

CC

GND

1OEAB

1LEAB

CC

V

1LEBA

1OEBA

1CEBA

GND

2A13

2B13

1B6

†

For HS package availability , please contact the factory or your local TI Field Sales Office.

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description

The ’ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage
of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit
transceiver. Separate latch-enable (LEAB

or LEBA) and output-enable (OEAB or OEBA) inputs are provided

for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB

) input must be low to enter data from A or to output data from B. If CEAB is low and

LEAB

is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and
OEBA inputs.

SN54ABTH32543, SN74ABTH32543

36-BIT REGISTERED BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS230F – JUNE 1992 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32543 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABTH32543 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

†

(each 18-bit section)

INPUTS

OUTPUT

CEAB LEAB OEAB A

B

H X X X Z
X XHXZ

L HLXB

0

‡

L LLLL
L L L H H

†

A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA

, LEBA, and OEBA.

‡

Output level before the indicated steady-state
input conditions were established