Datasheet SN74ABTH32543PZ Datasheet (Texas Instruments)

SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Widebus+
Family
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up and Power Down
D
Released as DSCC SMD 5962-9557801NXD
D
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package
767778798081828384858687888990919293949596979899100
494847464544434241403938373635343332313029282726
’ABTH32543 ...PZ PACKAGE
(TOP VIEW)
1A9
1A10
GND
1A1 1 1A12 1A13 1A14
GND 1A15 1A16 1A17 1A18
V
CC
2A1 2A2 2A3 2A4
GND
2A5 2A6 2A7 2A8
GND
2A9
2A10
1B9 1B10 GND 1B11 1B12 1B13 1B14 GND 1B15 1B16 1B17 1B18 V
CC
2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 2B8 GND 2B9 2B10
1A8
1A7
1A6
V
CC
GND
2A14
2A11
2A12
2A13
1A5
1A4
1A3
1A2
1A1
1CEBA
1OEBA
1LEBA
1LEAB
1OEAB
1CEAB
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
GND
2A18
2A15
2A16
2A17
2LEAB
2OEAB
2CEBA
2OEBA
2B16
2B15
2CEAB
2B18
2B17
GND
2B13
2B14
2B12
2B11
V
CC
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2LEBA
The HS package is not production released.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1B7 1B8
1B10 1B11
1B12 1B13 1B14 GND 1B15 1B16 1B17 1B18
2B1
2B4 GND 2B5 2B6 2B7 2B8
1A6 1A8
1A9
1A10 1A11
1A12 1A13 1A14
1A15 1A16
1A18
2A1 2A2 2A3 2A4
GND
2A5 2A7
2A8
GND
1A5
1A3
1A2
1A1
1B2
1B3
1B4
1B5
GND
GND
2A14
2A15
2A16
2A17
2A18
2CEBA
2B18
2B17
2B16
2B14
GND
2B15
1A7
1CEAB
1B9
2B3
GND
2A6
2A9 2A10 2A11 2A12
GND 2B9
2B10 2B11
2B12
1B1
1A4
SN54ABTH32543 . . . HS PACKAGE
(TOP VIEW)
1A17
V
CC
2OEBA
2LEBA
CC
V
2LEAB
2OEAB
2CEAB
2B2
V
CC
GND
1OEAB
1LEAB
CC
V
1LEBA
1OEBA
1CEBA
GND
2A13
2B13
1B6
For HS package availability , please contact the factory or your local TI Field Sales Office.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
description
The ’ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB
or LEBA) and output-enable (OEAB or OEBA) inputs are provided
for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB
) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH32543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32543 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 18-bit section)
INPUTS
OUTPUT
CEAB LEAB OEAB A
B
H X X X Z X XHXZ
L HLXB
0
L LLLL L L L H H
A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA
, LEBA, and OEBA.
Output level before the indicated steady-state input conditions were established
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
1B1
To 17 Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
2B1
To 17 Other Channels
Pin numbers shown are for the PZ package.
90
91
89 86
85
87
92
36
35
37 40
41
39
14
84
62
C1 1D
C1 1D
C1 1D
C1 1D
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH32543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH32543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): PZ package 50°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32543 SN74ABTH32543
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
t/v Input transition rise or fall rate Outputs enabled 10 10 ns/Vt/V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54ABTH32543 SN74ABTH32543
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V, IOH = – 3 mA 2.5 2.5 VCC = 5 V, IOH = – 3 mA 3 3
V
OH
IOH = – 24 mA 2
V
V
CC
=
4.5 V
IOH = – 32 mA 2 IOL = 48 mA 0.55 0.55
VOLV
CC
= 4.5
V
IOL = 64 mA 0.55
V
V
hys
100 100 mV Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20
I
I
Control inputs
±1
µ
A
A or B ports
V
CC
= 5.5 V,
V
I
=
V
CC
or
GND
±20
p
VI = 0.8 V 100
I
I(hold)
A or B ports
V
CC
= 4.5
V
VI = 2 V –100
µ
A
I
OZPU
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
I
OZPD
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
I
off
VCC = 0, VI or VO 4.5 V ±100 µA
I
CEX
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 µA
I
O
§
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –100 –180 mA
Outputs high 3 3
I
CC
VCC = 5.5 V, IO = 0,
Outputs low 20 20
mA
V
I
=
V
CC
or
GND
Outputs disabled 2 2
I
CC
VCC = 5.5 V , One input at 3.4 V, Other inputs at VCC or GND
1 1 mA
C
i
Control inputs VI = 2.5 V or 0.5 V 3.5 3.5 pF
C
io
A or B ports VO = 2.5 V or 0.5 V 9.5 9.5 pF
All typical values are at VCC = 5 V, TA = 25°C.
This parameter is specified by characterization.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
#
SN54ABTH32543 SN74ABTH32543
UNIT
MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LEAB or LEBA low 3.3 3.3 3.3 ns
p
Data before LEAB or LEBA 2.1 2.6 2.1
tsuSetup time
Data before CEAB or CEBA 1.7 2 1.7
ns
Data after LEAB or LEBA 0.6 1.1 0.6
thHold time
Data after CEAB or CEBA 0.9 1.2 0.9
ns
#
These limits apply only to the SN74ABTH32543.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABTH32543 SN74ABTH32543
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
t
PLH
1 3.5 5.2 0.5 6.3 1 5.9
t
PHL
A or B
B or A
1 3.5 5.1 0.5 5.9 1 5.7
ns
t
PLH
1.9 4.6 6.3 0.8 7.9 1.9 7.5
t
PHL
LE
A or B
1.9 4.3 5.9 0.8 6.9 1.9 6.6
ns
t
PZH
1.7 4.3 6.7 0.8 8.3 1.7 8
t
PZL
CE
A or B
2.6 5.2 8 1 8.8 2.6 8.8
ns
t
PHZ
1.6 3.8 6.6 0.5 7.4 1.6 7.1
t
PLZ
CE
A or B
2.4 4.6 7 1 7.9 2.4 7.5
ns
t
PZH
1.4 3.8 6.1 0.5 7.6 1.4 7.3
t
PZL
OE
A or B
2.3 4.7 7.4 1 8.2 2.3 8.1
ns
t
PHZ
1.3 3.4 6.1 0.5 6.7 1.3 6.5
t
PLZ
OE
A or B
2 4.2 6.6 0.8 7.2 2 6.9
ns
These limits apply only to the SN74ABTH32543.
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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