D
Members of the Texas Instruments
Widebus+
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
UBE
(Universal Bus Exchanger)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, TA = 25°C
CC
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 80-Pin Plastic
Thin Quad Flat (PN) Package With
12 × 12-mm Body Using 0.5-mm Lead Pitch
and 84-Pin Ceramic Quad Flat (HT) Package
A2
A3
A4
GND
A5
A6
A7
A8
A9
V
CC
GND
A10
A1 1
A12
A13
A14
GND
A15
A16
A17
A1
SELA
79 78 77 76 7580 74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
21
SN74ABTH32318 . . . PN PACKAGE
OEA
OEC
SELC
25 26 27 28
24
LEC
(TOP VIEW)
CLKC
C18
72 71 7073
29
GND
C17
VCCC16
30 31 32 33
69 68
C14
C13
C15
67 66 65 64
34 35 36 37
C12
GND
C1 1
63 62 61
38 39 40
C10
C9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C8
C7
C6
GND
C5
C4
C3
C2
C1
V
CC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B1 1
B1
A18
LEA
CLKA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
LEB
OEB
SELB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
B2
CLKB
V
CC
B3
GND
B5B6B7
B4
B8
B9
GND
B10
Copyright 1997, Texas Instruments Incorporated
1
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
A2
A3
A4
GND
A5
A6
A7
A8
A9
V
CC
NC
GND
A10
A1 1
A12
A13
A14
GND
A15
A16
A17
A1
SELA
83 82 81 80 7984 78
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23 24
22
SN54ABTH32318 ...HT PACKAGE
OEA
OEC
SELC
LEC
26 27 28 29
25
(TOP VIEW)
CLKC
C18
C17
76 75 7477
30 31 32 33 34
VCCGND
NC
73 72
C15
C14
C16
71 70 69 68
35 36 37 38
C13
C12
C10
GND
C1 1
67 66 65 64
39 40 41 42
C9
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
C8
C7
C6
GND
C5
C4
C3
C2
C1
V
CC
NC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B1 1
A18
LEA
OEB
CLKA
NC – No internal connection
LEB
SELB
B1
CLKB
B2
CC
V
NC
GND
B4B5B6
B3
B7
B8
GND
B10
B9
description
The ’ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type
latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be
exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations
of real-time and stored data can be exchanged among the three ports.
Data flow in each direction is controlled by the output-enable (OEA
SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data
register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held
at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data
selection is accomplished by the select-control pins. All three ports have active-low output enables, so when
the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in
the high-impedance state.
When V
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
, OEB, and OEC), select-control (SELA,
should be tied to VCC through a pullup resistor;
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
OUTPUT A
OUTPUT B
OUTPUT C
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
description (continued)
The SN54ABTH32318 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32318 is characterized for operation from –40°C to 85°C.
Function Tables
STORAGE
INPUTS
CLKA LEA A
↑ L L L
↑ LH H
H LX Q
L LX Q
X HL L
X HH H
†
A-port register shown. B and C ports are
similar but use CLKB, CLKC, LEB, and
LEC.
‡
Output level before the indicated
steady-state input conditions were
established
A-PORT OUTPUT
INPUTS
OEA SELA
H X Z
L H Output of C register
L L Output of B register
†
0
0
‡
‡
B-PORT OUTPUT
INPUTS
OEB SELB
H X Z
L H Output of A register
L L Output of C register
C-PORT OUTPUT
INPUTS
OEC SELC
H X Z
L H Output of B register
L L Output of A register
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
logic diagram (positive logic)
77
OEC
SELC
76
CLKC
LEC
C1
OEB
SELB
CLKB
LEB
B1
74
75
52
24
25
27
26
28
LE
LE
CLK
CLK
Q
D
Q
D
78
OEA
LEA
A1
79
22
23
80
SELA
CLKA
Pin numbers shown are for the PN package.
4
Q
CLK
LE
D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1 of 18 Channels
UNIT
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABTH32318 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
SN74ABTH32318 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 2): PN package 62°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABTH32318 SN74ABTH32318
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABTH32318, SN74ABTH32318
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
A
I
A, B, or C ports
V
V
A
V
CC
∆I
¶
CC
0.5
0.5
mA
UNIT
twPulse duration
ns
tsuSetup time
ns
thHold time
ns
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH32318 SN74ABTH32318
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
V
hys
I
I(hold)
I
OZPU
I
OZPD
I
off
I
CEX
I
O
I
CC
C
C
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is specified by characterization.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1
A, B, or C ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20 ±20
‡
‡
§
CC
Control inputs VI = 2.5 V or 0.5 V 3 3 pF
i
A, B, or C ports VO = 2.5 V or 0.5 V 11.5 11.5 pF
io
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3
=
CC
= 4.5
CC
p
= 4.5
CC
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –100 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55 0.55
100 100 mV
VI = 0.8 V 100 100
VI = 2 V –100 –100
Outputs high 2 2
Outputs low 45 45
Outputs disabled 1 1
µ
µ
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
f
clock
Clock frequency 150 150 MHz
p
SN54ABTH32318 SN74ABTH32318
MIN MAX MIN MAX
LE high 3.3 3.3
CLK high or low 3.3 3.3
A, B, or C before CLK↑ 2.4 2.4
A, B, or C before LE↓ 2.1 2.1
A, B, or C after CLK↑ 1.4 1.4
A, B, or C after LE↓ 2.1 2.1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
A, B, or C
C, B, or A
ns
SEL
A, B, or C
ns
LE
A, B, or C
ns
CLK
A, B, or C
ns
OE
A, B, or C
ns
OE
A, B, or C
ns
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM TO
(INPUT) (OUTPUT)
SN54ABTH32318 SN74ABTH32318
MIN MAX MIN MAX
150 150 MHz
1.4 6.5 1.4 6.1
1.1 6.8 1.1 6.6
1.4 6.7 1.4 6.5
1.8 6.8 1.8 6.5
2.6 8 2.6 7.5
2.6 7.4 2.6 6.9
2.5 8 2.5 7.4
2.5 7.2 2.5 6.7
1.4 6.9 1.4 6.8
2.4 7.2 2.4 7.1
1 6.4 1 6.2
2 6.4 2 6
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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