Texas Instruments SN74ABTH32318PN Datasheet
D
Members of the Texas Instruments
Widebus+
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
UBE
(Universal Bus Exchanger)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, TA = 25°C
CC
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 80-Pin Plastic
Thin Quad Flat (PN) Package With
12 × 12-mm Body Using 0.5-mm Lead Pitch
and 84-Pin Ceramic Quad Flat (HT) Package
A2
A3
A4
GND
A5
A6
A7
A8
A9
V
CC
GND
A10
A1 1
A12
A13
A14
GND
A15
A16
A17
A1
SELA
79 78 77 76 7580 74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
21
SN74ABTH32318 . . . PN PACKAGE
OEA
OEC
SELC
25 26 27 28
24
LEC
(TOP VIEW)
CLKC
C18
72 71 7073
29
GND
C17
VCCC16
30 31 32 33
69 68
C14
C13
C15
67 66 65 64
34 35 36 37
C12
GND
C1 1
63 62 61
38 39 40
C10
C9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C8
C7
C6
GND
C5
C4
C3
C2
C1
V
CC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B1 1
B1
A18
LEA
CLKA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
LEB
OEB
SELB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
B2
CLKB
V
CC
B3
GND
B5B6B7
B4
B8
B9
GND
B10
Copyright 1997, Texas Instruments Incorporated
1
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
A2
A3
A4
GND
A5
A6
A7
A8
A9
V
CC
NC
GND
A10
A1 1
A12
A13
A14
GND
A15
A16
A17
A1
SELA
83 82 81 80 7984 78
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23 24
22
SN54ABTH32318 ...HT PACKAGE
OEA
OEC
SELC
LEC
26 27 28 29
25
(TOP VIEW)
CLKC
C18
C17
76 75 7477
30 31 32 33 34
VCCGND
NC
73 72
C15
C14
C16
71 70 69 68
35 36 37 38
C13
C12
C10
GND
C1 1
67 66 65 64
39 40 41 42
C9
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
C8
C7
C6
GND
C5
C4
C3
C2
C1
V
CC
NC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B1 1
A18
LEA
OEB
CLKA
NC – No internal connection
LEB
SELB
B1
CLKB
B2
CC
V
NC
GND
B4B5B6
B3
B7
B8
GND
B10
B9
description
The ’ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type
latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be
exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations
of real-time and stored data can be exchanged among the three ports.
Data flow in each direction is controlled by the output-enable (OEA
SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data
register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held
at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data
selection is accomplished by the select-control pins. All three ports have active-low output enables, so when
the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in
the high-impedance state.
When V
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
, OEB, and OEC), select-control (SELA,
should be tied to VCC through a pullup resistor;
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
OUTPUT A
OUTPUT B
OUTPUT C
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MA Y 1997
description (continued)
The SN54ABTH32318 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32318 is characterized for operation from –40°C to 85°C.
Function Tables
STORAGE
INPUTS
CLKA LEA A
↑ L L L
↑ LH H
H LX Q
L LX Q
X HL L
X HH H
†
A-port register shown. B and C ports are
similar but use CLKB, CLKC, LEB, and
LEC.
‡
Output level before the indicated
steady-state input conditions were
established
A-PORT OUTPUT
INPUTS
OEA SELA
H X Z
L H Output of C register
L L Output of B register
†
0
0
‡
‡
B-PORT OUTPUT
INPUTS
OEB SELB
H X Z
L H Output of A register
L L Output of C register
C-PORT OUTPUT
INPUTS
OEC SELC
H X Z
L H Output of B register
L L Output of A register
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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