D
Members of the Texas Instruments
Widebus+
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Released as DSCC SMD 5962-9557701NXD
D
PZ Package Qualified for Military Per
MIL-PRF-38535 (QML)
SN54ABTH32245, SN74ABTH32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14 × 14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package
†
1A9
2A1
GND
2A2
2A3
2A4
2A5
GND
2A6
2A7
2A8
2A9
V
CC
3A1
3A2
3A3
3A4
GND
3A5
3A6
3A7
3A8
GND
3A9
4A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1A8
1A7
1A6
1A5
GND
’ABTH32245 ...PZ PACKAGE
1A4
1A3
1A2
(TOP VIEW)
1A1
GND
1DIR
1OE
V
CC
2OE
2DIR
GND
1B1
1B2
1B3
1B4
1B5
GND
1B6
494847464544434241403938373635343332313029282726
1B7
767778798081828384858687888990919293949596979899100
50
1B8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B9
2B1
GND
2B2
2B3
2B4
2B5
GND
2B6
2B7
2B8
2B9
V
CC
3B1
3B2
3B3
3B4
GND
3B5
3B6
3B7
3B8
GND
3B9
4B1
4A3
4A5
4A4
4A6
4A7
4A9
GND
4A8
GND
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4A2
†
The HS package is not production released.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
4OE
4DIR
V
CC
3OE
3DIR
4B9
GND
4B8
4B7
4B6
4B4
4B5
4B3
GND
4B2
Copyright 1997, Texas Instruments Incorporated
1
SN54ABTH32245, SN74ABTH32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
1A6
1A7
1A8
1A9
2A1
GND
2A2
2A3
2A4
2A5
GND
2A6
2A7
2A8
2A9
V
CC
3A1
3A2
3A3
3A4
GND
3A5
3A6
3A7
3A8
GND
3A9
4A1
4A2
4A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SN54ABTH32245 . . . HS PACKAGE
1A4
GND
1A5
1A3
1A2
96
97
98
99
100
35
34
33
32
31
1A1
95
36
GND
94
37
(TOP VIEW)
CC
1DIR
1OE
V
91
92
93
40
39
38
2OE
90
41
2DIR
88
89
43
42
GND
1B1
87
44
1B2
86
45
†
1B3
85
46
1B4
84
47
1B5
83
48
GND
1B6
81
82
50
49
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B7
1B8
1B9
2B1
GND
2B2
2B3
2B4
2B5
GND
2B6
2B7
2B8
2B9
V
CC
3B1
3B2
3B3
3B4
GND
3B5
3B6
3B7
3B8
GND
3B9
4B1
4B2
4B3
4B4
4A4
4A5
4A6
4A7
4A8
4A9
GND
†
For HS package availability , please contact the factory or your local TI Field Sales Office.
GND
4OE
4DIR
CC
V
3OE
3DIR
4B9
GND
4B8
4B7
4B6
4B5
GND
description
The ’ABTH32245 are 36-bit (quad 9-bit) noninverting 3-state transceivers designed for synchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
These devices can be used as four 9-bit transceivers, two18-bit transceivers, or one 36-bit transceiver. They
allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level
at the direction-control (DIR) inputs. The output-enable (OE) inputs can be used to disable the device so that
the buses are effectively isolated.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OPERATION
SN54ABTH32245, SN74ABTH32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
description (continued)
The SN54ABTH32245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
DIR
OE
L L B data to A bus
L H A data to B bus
H X Isolation
logic diagram (positive logic)
1DIR
1A1
2DIR
2A1
90
92
86
2
One of Nine
Channels
To Eight Other Channels
One of Nine
Channels
89
84
87
74
1OE
1B1
2OE
2B1
3DIR
3A1
4DIR
4A1
40
14
36
25
One of Nine
Channels
To Eight Other Channels
One of Nine
Channels
39
62
37
51
3OE
3B1
4OE
4B1
To Eight Other Channels
Pin numbers shown are for the PZ package.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
To Eight Other Channels
3
SN54ABTH32245, SN74ABTH32245
UNIT
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH32245 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): PZ package 50°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABTH32245 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABTH32245 SN74ABTH32245
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
A
I
V
V
V
GND
A
I
A or B ports
V
V
A
V
CC
(INPUT)
(OUTPUT)
A or B
B or A
ns
OE
B or A
ns
OE
B or A
ns
SN54ABTH32245, SN74ABTH32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH32245 SN74ABTH32245
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
V
hys
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1
I
I(hold)
I
OZPU
I
OZPD
I
off
I
CEX
I
O
I
CC
∆I
C
C
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is specified by characterization.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20
Control inputs
A or B ports
p
‡
‡
§
¶
CC
Control inputs VI = 2.5 V or 0.5 V 3.5 3.5 pF
i
A or B ports VO = 2.5 V or 0.5 V 9.5 9.5 pF
io
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
= 4.5
CC
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –100 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55
100 100 mV
=
or
I
CC
VI = 0.8 V 100 100
VI = 2 V –100 –100
Outputs high 3 3
Outputs low 20 20
Outputs disabled 2 2
±1
±20
1 1 mA
µ
µ
µ
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
#
PLZ
These limits apply only to the SN74ABTH32245
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1.7 3.2 4.4 1 5.3 1.7 5
1.7 3.3 4.6 1 5.3 1.7 5.2
1.6 4.2 6.1 1 7.6 1.6 7.3
2.7 5.2 7 1.5 8.2 2.7 8.1
1.3 3.9 6.1 0.8 6.7 1.3 6.5
2 4.4 6.6 1 7.2 2 6.9
#
SN54ABTH32245 SN74ABTH32245
UNIT
5
SN54ABTH32245, SN74ABTH32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228G – JUNE 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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