Texas Instruments SN74ABTH25245DW, SN74ABTH25245DWR, SN74ABTH25245NT Datasheet
SN54ABTH25245, SN74ABTH25245
25-Ω OCT AL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS251F – JUNE 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 25 Ω or
Greater
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and Standard Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABTH25245 are 25-Ω octal bus transceivers
designed for asynchronous communication
between data buses. They improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
transceivers.
These devices allow noninverted data
transmission from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The
output-enable (OE
) input can disable the device
so that both buses are effectively isolated. When
OE
is low, the device is active.
These transceivers are capable of sinking 188 mA of I
OL
current, which facilitates switching 25-Ω transmission
lines on the incident wave. The distributed V
CC
and GND pins minimize switching noise for more-reliable system
operation.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A1
GND
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
DIR
B1
B2
V
CC
B3
B4
B5
B6
V
CC
B7
B8
OE
SN54ABTH25245 . . . JT PACKAGE
SN74ABTH25245 . . . DW OR NT PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
OE
A8
GND
NC
A7
A6
GND
B3
V
CC
B2
NC
B1
DIR
A1
426
14 15 16 17
18
GND
A2
A3
NC
GND
A4
A5
B4B5B6NCVB7B8
SN54ABTH25245 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
SN54ABTH25245, SN74ABTH25245
25-Ω OCT AL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS251F – JUNE 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH25245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH25245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
B2
22
B3
20
B4
19
A5
7
A6
9
A7
10
A8
12
A2
3
A3
4
A4
6
OE
A1
1
G3
13
3 EN2 [AB]
B5
18
B6
17
B7
15
B8
14
B1
23
3 EN1 [BA]
24
DIR
1
2
SN54ABTH25245, SN74ABTH25245
25-Ω OCT AL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS251F – JUNE 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
DIR
OE
A1
B1
To Seven Other Channels
24
1
13
23
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
–0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN74ABTH25245 (A port) 376 mA. . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH25245 (B port) 128 mA. . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
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