Datasheet SN74ABTH16823DLR, SN74ABTH16823DGGR, SN74ABTH16823DL Datasheet (Texas Instruments)
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
T ypical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The ’ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN
) input
low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the
clock buffer , latching the outputs. T aking the clear (CLR) input low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABTH16823 . . . WD PACKAGE
SN74ABTH16823 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH16823 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16823 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
OUTPUT
OE
CLR CLKEN
CLK D
Q
L L X X X L
L HL↑ HH
L HL↑ LL
L HLLX Q
0
L HHXX Q
0
H X X X X Z
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN1
2
56
1CLK 3C4
4D
54
1D1 1Q1
3
52
1D2 1Q2
5
51
1D3 1Q3
6
49
1D4
1Q4
8
48
1D5
1Q5
9
47
1D6
1Q6
10
45
1D7
1Q7
12
44
1D8
1Q8
13
43
1D9 1Q9
14
1, 2
8D
42
2D1 2Q1
15
41
2D2
2Q2
16
40
2D3 2Q3
17
38
2D4
2Q4
19
37
2D5
2Q5
20
36
2D6
2Q6
21
34
2D7 2Q7
23
33
2D8 2Q8
24
31
2D9 2Q9
26
5, 6
R2
1
G3
55
EN5
27
29
2CLK
7C8
R6
28
G7
30
1OE
1CLR
1CLKEN
2OE
2CLR
2CLKEN
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
To Eight Other Channels
1D1
1Q1
1CLKEN
1OE
1CLR
2
1
55
54
R
1D
C1
3
CE
56
1CLK
To Eight Other Channels
2D1
2Q1
2CLKEN
2OE
2CLR
27
28
30
42
R
1D
C1
15
CE
29
2CLK
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH16823 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH16823 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABTH16823 SN74ABTH16823
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABTH16823 SN74ABTH16823
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
V
OH
IOH = –24 mA 2 2
V
V
CC
=
4.5 V
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
VOLV
CC
= 4.5
V
IOL = 64 mA 0.55* 0.55
V
V
hys
100 mV
I
I
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VI = 0.8 V 100 100 100
I
I(hold)
V
CC
= –4.5
V
VI = 2 V –100 –100 –100
µ
A
I
OZPU
‡
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
OZPD
‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
OZH
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
≥ 2 V
10** 50 10 µA
I
OZL
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
≥ 2 V
–10** –50 –10 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
I
O
§
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
Outputs high 0.5 0.5 0.5
Outputs low
VCC = 5.5 V, IO = 0,
80 80 80
I
CC
Outputs
disabled
VI = VCC or GND
0.5 0.5 0.5
mA
∆I
CC
¶
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1.5 1.5 1.5 mA
C
i
VI = 2.5 V or 0.5 V 4 pF
C
o
VO = 2.5 V or 0.5 V 8.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABTH16823.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
SN54ABTH16823 SN74ABTH16823
UNIT
MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency 0 150 0 150 0 150 MHz
CLR low 3.3 3.3 3.3
twPulse duration
CLK high or low 3.3 3.3 3.3
ns
CLR inactive 1.6 2 1.6
t
su
Setup time before CLK↑
Data
1.7 1.7 1.7
ns
CLKEN low 2.8 2.8 2.8
Data 1.2 1.2 1.2
t
h
Hold ti
me after
CLK↑
CLKEN low 0.6 0.6 0.6
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
SN54ABTH16823
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN MAX
UNIT
MIN TYP MAX
f
max
150 150 MHz
t
PLH
1.6 3.9 5.5 1.6 7.7
t
PHL
CLK
Q
2.1 3.9 5.4 2.1 6.4
ns
t
PHL
CLR
Q 1.9 4.1 6 1.9 6.9 ns
t
PZH
1 3.1 4.2 1 5.1
t
PZL
OE
Q
1.5 3.5 4.6 1.5 5.7
ns
t
PHZ
2.2 4.3 6 2.2 6.8
t
PLZ
OE
Q
1.6 4.3 6.4 1.6 9.9
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
SN74ABTH16823
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN MAX
UNIT
MIN TYP MAX
f
max
150 150 MHz
t
PLH
1.6 3.9 5.5 1.6 6.8
t
PHL
CLK
Q
2.1 3.9 5.4 2.1 6
ns
t
PHL
CLR
Q 1.9 4.1 6 1.9 6.7 ns
t
PZH
1 3.1 4.2 1 4.9
t
PZL
OE
Q
1.5 3.5 4.6 1.5 5.5
ns
t
PHZ
2.2 4.3 5.6 2.2 6.1
t
PLZ
OE
Q
1.6 4.3 6.4 1.6 8.7
ns
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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