Texas Instruments SN74ABTH16460DGGR, SN74ABTH16460DL, SN74ABTH16460DLR Datasheet
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABTH16460 are 4-bit to 1-bit multiplexed
registered transceivers used in applications
where four separate data paths must be
multiplexed onto or demultiplexed from a single
data path. Typical applications include
multiplexing and/or demultiplexing of address and
data information in microprocessor or
bus-interface applications. These devices also
are useful in memory-interleaving applications.
Five 4-bit I/O ports (1A–4A, 1B1–4, 2B1–4, 3B1–4, and 4B1–4) are available for address and/or data transfer.
The output-enable (OEB
, OEB1–OEB4, and OEA) inputs control the bus-transceiver functions. These control
signals also allow 4-bit or 16-bit control, depending on the OEB level.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABTH16460 . . . WD PACKAGE
SN74ABTH16460 . . . DGG OR DL PACKAGE
(TOP VIEW)
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LEAB1
LEAB2
LEBA
GND
LEB1
LEB2
V
CC
CLKBA
OEB
CLKAB
GND
1A
2A
CE_SEL0
CE_SEL1
3A
4A
GND
CLKENAB
CLKENB
CLKENBA
V
CC
LEB3
LEB4
GND
OEA
LEAB3
LEAB4
OEB1
OEB2
SEL0
GND
1B1
1B2
V
CC
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
V
CC
4B3
4B4
GND
SEL1
OEB3
OEB4
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable
(LEB1–LEB4, LEBA, and LEAB1–LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data
storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don’t care as long
as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from
low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned
high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the
low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the
clock is a don’t care.
Four select pins (SEL0, SEL1, CE_SEL0, and CE_SEL1) are provided to multiplex data (A port), or to select
one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH16460 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16460 is characterized for operation from –40°C to 85°C.
Function Tables
A-TO-B OUTPUT ENABLE
†
INPUTS
OUTPUT
OEB OEBn
Bn
H H Z
H LZ
L HZ
L L Active
†
n = 1, 2, 3, 4
A-TO-B STORAGE
(assuming OEB
= L, OEBn = L)
‡
INPUTS
OUTPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4 B1 B2 B3 B4
X X X H or L H L L L A A
0
A
0
A
0
X X X H or L H H H L A AAA
0
L X X L LLLLA0A
0
A
0
A
0
L LL↑ LLLLAA
0
A
0
A
0
L LH↑ LLLLA0AA0A
0
L HL↑ LLLLA0A
0
AA
0
L HH↑ LLLLA0A
0
A
0
A
H X X ↑ L L L L A
0
A
0
A
0
A
0
‡
This table does not cover all the latch-enable cases since they have similar results.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
B-TO-A STORAGE
(before point P)
INPUTS
CLKENB
CLKBA LEB1 LEB2 LEB3 LEB4 SEL1 SEL0
P
X X H L L L L L B1
X XLHLLLHB2
X X LLHLHLB3
X XLLLHHHB4
L L B1
L HB2
L↑LLL
L
H LB3
H HB4
L L B1
0
†
L HB2
0
†
LLLLL
L
H LB3
0
†
H H B4
0
†
†
Output level before the indicated steady-state input conditions were established
B-TO-A STORAGE
(after point P)
INPUTS
OUTPUT
CLKENBA
CLKBA LEBA
OEA
B
A
X X X H X Z
X XHLL L
X XHLH H
H XLLXA
0
†
L ↑ LLL L
L ↑ LLH H
L L L L X A
0
†
†
Output level before the indicated steady-state input conditions
were established
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