SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
The ’ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data
paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include
multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface
applications. These devices are also useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
SN54ABTH162260 ...WD PACKAGE
SN74ABTH162260 . . . DL PACKAGE
(TOP VIEW)
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OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
LEA1B
OE1B
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH162260 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABTH162260 is characterized for operation from –40°C to 85°C.
Function Tables
B TO A (OEB = H)
INPUTS
OUTPUT
1B 2B SEL LE1B LE2B OEA
A
H X H H X L H
L XHHXL L
X XHLXL A
0
X HLXHL H
X LLXHL L
X XLXLL A
0
X X X X X H Z
A TO B (OEA = H)
INPUTS
OUTPUTS
A LEA1B LEA2B OE1B OE2B 1B 2B
H H H L L H H
L HHLLLL
H HLLLH2B
0
L HLLLL2B
0
H LHLL1B0H
L LHLL1B0L
X LLLL1B02B
0
X XXHHZZ
X X X L H Active Z
X XXHLZActive
X X X L L Active Active
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1D
C1
1D
C1
1D
C1
1D
To 11 Other Channels
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
1B1
2B1
27
2
30
55
56
29
1
28
8
23
6
G1
1
1
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH162260 (A port) 96 mA. . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH162260 (A port) 128 mA. . . . . . . . . . . . . . . . . . . . . . . .
B port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH162260 SN74ABTH162260
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
p
A port 48 64
IOLLow-level output current
B port 12 12
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABTH162260 SN74ABTH162260
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
V
OH
IOH = –24 mA 2 2
V
V
CC
=
4.5 V
IOH = –32 mA 2* 2
p
IOL = 48 mA 0.55 0.55
V
OL
A port
VCC = 4.5 V
IOL = 64 mA 0.55* 0.55
V
B port IOL = 12 mA 0.8 0.8 0.8
V
hys
100 mV
Control
inputs
VCC = 0 to 5.5 V,
VI = VCC or GND
±1 ±1 ±1
I
I
A or B ports
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
±20 ±20 ±20
µ
A
p
VI = 0.8 V 100
I
I(hold)
A or B ports
V
CC
=
4.5 V
VI = 2 V –100
µ
A
I
OZPU
‡
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
OZPD
‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
OZH
§
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
≥ 2 V
10 10 10 µA
I
OZL
§
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
≥ 2 V
–10 –10 –10 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
I
O
¶
VCC = 5.5 V, VO = 2.5 V –50 –100 –225 –50 –225 –50 –225 mA
Outputs high 1.5 1.5 1.5
Outputs low
VCC = 5.5 V, IO = 0,
63 63 63
I
CC
Outputs
disabled
VI = VCC or GND
1 1 1
mA
∆I
CC
#
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1 1.5 1 mA
C
i
VI = 2.5 V or 0.5 V 3 pF
C
o
VO = 2.5 V or 0.5 V 11.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized but not tested.
§
The parameters I
OZH
and I
OZL
include the input leakage current.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
SN54ABTH162260 SN74ABTH162260
UNIT
MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 3.3 3.3 ns
t
su
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓ 1.5 1.5 1.5 ns
t
h
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓ 1 1 1 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABTH162260 SN74ABTH162260
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
t
PLH
1.4 3.6 5.2 1.4 6.3 1.4 6.1
t
PHL
A
B
2.7 4.8 6.4 2.7 7.4 2.7 7.1
ns
t
PLH
1.6 3.6 5.2 1.6 6.4 1.6 6
t
PHL
B
A
1.7 3.8 5.5 1.7 6.5 1.7 6.2
ns
t
PLH
1.8 3.9 5.3 1.8 6.6 1.8 6.3
t
PHL
LE
A
2.3 4.1 5.4 2.3 6.1 2.3 5.8
ns
t
PLH
1.6 3.7 5.4 1.6 6.4 1.6 6.1
t
PHL
LE
B
2.8 4.9 6.4 2.8 7.5 2.8 7.1
ns
t
PLH
1.5 3.6 5 1.5 5.9 1.5 5.6
t
PHL
SEL (1B)
A
1.8 3.5 4.8 1.8 5.2 1.8 5
ns
t
PLH
1.2 3.6 5.1 1.2 6.5 1.2 6.3
t
PHL
SEL (2B)
A
1.7 4 5.5 1.7 6.5 1.7 6.2
ns
t
PZH
1.1 3.5 5.2 1.1 6.5 1.1 6.3
t
PZL
OE
A
2.1 4.2 5.7 2.1 6.6 2.1 6.5
ns
t
PZH
1 3.4 4.9 1 6.4 1 6.3
t
PZL
OE
B
2.9 5.5 6.8 2.9 8.3 2.9 8.2
ns
t
PHZ
2.5 4.5 5.9 2.5 6.9 2.5 6.7
t
PLZ
OE
A
1.8 3.4 4.8 1.8 5.6 1.8 5.2
ns
t
PHZ
2.1 4.4 5.7 2.1 7.7 2.1 7.5
t
PLZ
OE
B
1.7 3.9 5.4 1.7 6.3 1.7 6.2
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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