Datasheet SN74ABT853DBLE, SN74ABT853DBR, SN74ABT853DW, SN74ABT853DWR, SN74ABT853NT Datasheet (Texas Instruments)

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

T ypical V

OLP

(Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

High-Impedance State During Power Up
and Power Down

D

Parity-Error Flag With Parity
Generator/Checker

D

Latch for Storage of Parity-Error Flag

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

The ’ABT853 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR

) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR

flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OEA

A1
A2
A3
A4
A5
A6
A7
A8

ERR

CLR

GND

V

CC

B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE

SN54ABT853 . . . JT OR W PACKAGE

SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

B3
B4
B5
NC
B6
B7
B8

A3
A4
A5

NC

A6
A7
A8

426

14 15 16 1718

ERR

CLR

GND

NC

LE

OEB

PARITY

A2A1OEANCB1

B2

SN54ABT853 . . . FK PACKAGE

(TOP VIEW)

V

CC

NC – No internal connection

SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT853 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS AND I/Os

OEB OEA CLR

LE

Ai

Σ OF H

Bi

†

Σ OF H

A B PARITY

ERR

‡

FUNCTION

Odd

L

A data to B bus and

LHX

X

Even

NANAAHNA

generate parity

Odd

H

B data to A bus and

HLXLNA

Even

BNANA

L

check parity

H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error flag register

H H X NC
LH X

H

Isolation

§

H

H

X L L Odd

XZZ

Z

H

(parity check)

X L H Even L

Odd

H

A data to B bus and

LLX

X

Even

NANAALNA

generate inverted parity

NA = not applicable, NC = no change, X = don’t care
†

Summation of high-level inputs includes PARITY along with Bi inputs.

‡

Output states shown assume ERR

was previously high.

§

In this mode, ERR

(when clocked) shows inverted parity of the A bus.

logic symbol

¶

ERR

CLR
OEA
OEB

CLR

11

1

2

A1

3

A2

4

A3

5

A4

10

PARITY

15

PARITY

B5

19

B6

18

B7

17

B8

16

8

OEA

1

OEB

14

6

A5

7

A6

8

A7

8

9

A8

B1

23

1

B2

22

B3

21

B4

20

ERR

Φ

A Bus B Bus

LE

LE

13

¶

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW , and W packages.

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

PARITY

ERR

CLR

B1–B8

A1–A8

LE

OEA

OEB

EN

EN

8x

8x

MUX

1

1
G1

1

1

2k

P

8

9

8

8

8

8

Pin numbers shown are for the DB, DW, JT, NT, PW , and W packages.

2–9

14

1

13
11

23–16

15

10

ERROR-FLAG FUNCTION TABLE

INPUTS

INTERNAL

TO DEVICE

OUTPUT

PRESTATE

OUTPUT

FUNCTION

CLR LE POINT P ERR

N–1

†

ERR

L

L

L

LHXHPass

L X L

H L

X

LL

Sample

H HH

L H X X H Clear

L L

HHX

H H

Store

†

The state of ERR before changes at CLR, LE, or point P

SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

error-flag waveforms

ERR

CLR

LE

OEA

OEB

Bi + PARITY

H
L

H
L

Even

Odd

H
L

H
L

H
L

Pass Store Sample

Clear

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I

O

: SN54ABT853 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT853 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ABT853 SN74ABT853

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

V

OH

High-level output voltage ERR 5.5 5.5 V

I

OH

High-level output current Except ERR –24 –32 mA

I

OL

Low-level output current 48 64 mA

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT853 SN74ABT853

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5

All outputs

VCC = 5 V, IOH = –3 mA 3 3 3

V

OH

except ERR

IOH = –24 mA 2 2

V

V

CC

=

4.5 V

IOH = –32 mA 2* 2
IOL = 24 mA 0.55 0.55

VOLV

CC

= 4.5

V

IOL = 64 mA 0.55* 0.55

V

V

hys

100 mV

I

OH

ERR VCC = 4.5 V, VOH = 5.5 V 50 50 50 µA
Control inputs

±1 ±1 ±1

I

I

A or B ports

V

CC

= 5.5 V,

V

I

=

V

CC

or

GND

±100 ±100 ±100

µ

A

I

OZPU

‡

VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE

= X

±50 ±50 ±50 µA

I

OZPD

‡

VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE

= X

±50 ±50 ±50 µA

I

OZH

§

VCC = 5.5 V, VO = 2.7 V 10 10 10 µA

I

OZL

§

VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

VCC = 5.5 V,
VO = 5.5 V

Outputs high 50 50 50 µA

I

O

¶

VCC = 5.5 V, VO = 2.5 V –50 –100 –200#–50 –200#–50 –200#mA
V

= 5.5 V

,

Outputs high 1 250 450 250 µA

I

CC

A or B ports

V

CC

5.5 V,

IO = 0,

Outputs low 24 38 38 38 mA

VI = VCC or GND

Outputs disabled 0.5 250 450 250 µA

VCC = 5.5 V,
One input at 3.4 V ,

Outputs enabled 1.5 1.5 1.5 mA

∆I

CC

||

D

ata inputs

,

Other inputs at
VCC or GND

Outputs disabled 50 50 50 µA

Control inputs

VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND

1.5 1.5 1.5 mA

C

i

Control inputs VI = 2.5 V or 0.5 V 4.5 pF

C

io

A or B ports VO = 2.5 V or 0.5 V 10.5 pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

The parameters I

OZH

and I

OZL

include the input leakage current.

¶

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

#

This data sheet limit can vary among suppliers.

||

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

VCC = 5 V,

TA = 25°C

SN54ABT853 SN74ABT853

UNIT

MIN MAX MIN MAX MIN MAX

LE high or low 3.5 3.5 3.5

twPulse duration

CLR low 4 4 4

ns

p

B or PARITY before LE↓ 9.4

†

10.2 9.4

†

tsuSetup time

CLR before LE↓ 2 2 2

ns

B or PARITY after LE↓ 0 0 0

thHold time

CLR after LE↓ 3 3 3

ns

†

This data sheet limit can vary among suppliers.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC = 5 V,

TA = 25°C

SN54ABT853 SN74ABT853

UNIT

(INPUT)

(OUTPUT)

MIN TYP MAX MIN MAX MIN MAX

t

PLH

1.2 4.8 1.2 6.4 1.2 5.3

t

PHL

A or B

B or A

1 4.8

†

1 5.4 1 5.3

†

ns

t

PLH

2.1 9.5 2.1 13.3 2.1 11.2

t

PHL

A

PARITY

2.5 9.7 2.5 11 2.5 11

ns

t

PLH

1.8 8.5 1.8 13.6 1.8 10.5

t

PHL

OE

PARITY

2.3 8.6 2.3 11.7 2.3 10

ns

t

PLH

CLR ERR

1 5.5 1 6.3 1 6.2 ns

t

PLH

1.8 5.1 1.8 6.1 1.8 6

t

PHL

LE

ERR

1

†

5.8 1

†

6.7 1 6.6

ns

t

PLH

2 10.1 2 11.8 2 11.7

t

PHL

B or PARITY

ERR

2.2

†

11.5 2.2†12.9 2.2†12.8

ns

t

PZH

1 5.8

†

1 8.8 1 6.7

†

t

PZL

OE

A or B or PARITY

1.5

†

5.8 1.5

†

9.8 1.5

†

6.7

ns

t

PHZ

1.8

†

7.3 1.8

†

9.5 1.8

†

7.9

t

PLZ

OE

A or B or PARITY

2.1

†

7.2 2.1

†

8.2 2.1

†

8.1

ns

†

This data sheet limit can vary among suppliers.

SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

1.5 V

t

h

t

su

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V 1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns

.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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