Texas Instruments SN74ABT853DBLE, SN74ABT853DBR, SN74ABT853DW, SN74ABT853DWR, SN74ABT853NT Datasheet

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

T ypical V

OLP

(Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

High-Impedance State During Power Up
and Power Down

D

Parity-Error Flag With Parity
Generator/Checker

D

Latch for Storage of Parity-Error Flag

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

The ’ABT853 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR

) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR

flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OEA

A1
A2
A3
A4
A5
A6
A7
A8

ERR

CLR

GND

V

CC

B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE

SN54ABT853 . . . JT OR W PACKAGE

SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

B3
B4
B5
NC
B6
B7
B8

A3
A4
A5

NC

A6
A7
A8

426

14 15 16 1718

ERR

CLR

GND

NC

LE

OEB

PARITY

A2A1OEANCB1

B2

SN54ABT853 . . . FK PACKAGE

(TOP VIEW)

V

CC

NC – No internal connection

SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT853 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS AND I/Os

OEB OEA CLR

LE

Ai

Σ OF H

Bi

†

Σ OF H

A B PARITY

ERR

‡

FUNCTION

Odd

L

A data to B bus and

LHX

X

Even

NANAAHNA

generate parity

Odd

H

B data to A bus and

HLXLNA

Even

BNANA

L

check parity

H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error flag register

H H X NC
LH X

H

Isolation

§

H

H

X L L Odd

XZZ

Z

H

(parity check)

X L H Even L

Odd

H

A data to B bus and

LLX

X

Even

NANAALNA

generate inverted parity

NA = not applicable, NC = no change, X = don’t care
†

Summation of high-level inputs includes PARITY along with Bi inputs.

‡

Output states shown assume ERR

was previously high.

§

In this mode, ERR

(when clocked) shows inverted parity of the A bus.

logic symbol

¶

ERR

CLR
OEA
OEB

CLR

11

1

2

A1

3

A2

4

A3

5

A4

10

PARITY

15

PARITY

B5

19

B6

18

B7

17

B8

16

8

OEA

1

OEB

14

6

A5

7

A6

8

A7

8

9

A8

B1

23

1

B2

22

B3

21

B4

20

ERR

Φ

A Bus B Bus

LE

LE

13

¶

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW , and W packages.

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

PARITY

ERR

CLR

B1–B8

A1–A8

LE

OEA

OEB

EN

EN

8x

8x

MUX

1

1
G1

1

1

2k

P

8

9

8

8

8

8

Pin numbers shown are for the DB, DW, JT, NT, PW , and W packages.

2–9

14

1

13
11

23–16

15

10

ERROR-FLAG FUNCTION TABLE

INPUTS

INTERNAL

TO DEVICE

OUTPUT

PRESTATE

OUTPUT

FUNCTION

CLR LE POINT P ERR

N–1

†

ERR

L

L

L

LHXHPass

L X L

H L

X

LL

Sample

H HH

L H X X H Clear

L L

HHX

H H

Store

†

The state of ERR before changes at CLR, LE, or point P