Datasheet SN74ABT843DBLE, SN74ABT843DBR, SN74ABT843DW, SN74ABT843DWR, SN74ABT843NT Datasheet (Texas Instruments)
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SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
description
The ’ABT843 9-bit latches are designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The nine transparent D-type latches provide true
data at the outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are also in the
high-impedance state during power-up and
power-down conditions. The outputs remain in the
high-impedance state while the device is powered
down. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
SN54ABT843 . . . JT OR W PACKAGE
SN74ABT843 . . . DB, DW, OR NT P ACKAGE
SN54ABT843 . . . FK PACKAGE
3D
4D
5D
NC
6D
7D
8D
NC – No internal connection
(TOP VIEW)
1
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
(TOP VIEW)
2D1DOE
426
3212827
5
6
7
8
9
10
11
12 13
9D
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CC
NC
V
14 15 16 17 18
LE
NC
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
1Q
PRE
2Q
25
24
23
22
21
20
19
9Q
3Q
4Q
5Q
NC
6Q
7Q
8Q
OE
does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT843 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT843 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
FUNCTION TABLE
INPUTS
PRE CLR OE LE D
L X L X X H
H LLXX L
H HLHL L
H HLHH H
H HLLX Q
X X H X X Z
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
†
OE
PRE
CLR
LE
1D
2D
3D
4D
5D
6D
7D
8D
9D
1
14
11
13
2
3
4
5
6
7
8
9
10
EN
S2
R
C1
1D
2
23
22
21
20
19
18
17
16
15
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
OE
14
PRE
11
CLR
13
LE
2
1D
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
9-BIT BUS-INTERFACE D-TYPE LATCHES
S2
C1
1D
R
To Eight Other Channels
SN54ABT843, SN74ABT843
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
23
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range , VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, I
: SN54ABT843 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ABT843 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
†
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3
SN54ABT843, SN74ABT843
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
4.5 V
V
V
I
V
CC
GND
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT843 SN74ABT843
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 5 5 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
TA = 25°C SN54ABT843 SN74ABT843
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
OL
V
hys
I
I
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
CC
C
i
C
o
§
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
= 4.5
CC
=
CC
VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
‡
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
‡
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = Open,
=
VCC = 5.5 V, One input at 3.4 V,
¶
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 4 pF
VO = 2.5 V or 0.5 V 7 pF
and I
OZH
IOH = –24 mA 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55
IOL = 64 mA 0.55* 0.55
100 mV
Outputs high 1 250 250 250 µA
or
include the input leakage current.
OZL
Outputs low 24 34 34 34 mA
Outputs disabled 0.5 250 250 250 µA
1.5 1.5 1.5 mA
CC
0 V
CC
V
4
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Data before LE↓
tsuSetup time
ns
thHold time, data after LE↓
ns
(INPUT)
(OUTPUT)
D
Q
ns
LE
Q
ns
PRE
Q
ns
CLR
Q
ns
OE
Q
ns
OE
Q
ns
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 and 2)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
CLR low 5.5 5.5 5.5
t
w
†
This data sheet limit may vary among suppliers.
Pulse duration
p
PRE
low 4.5 4.5 4.5
LE low 3.3 3.3 3.4
Low 2.5 2.5 2.5
High 3 3 3
PRE inactive 1.6 1.6 1.6
CLR inactive 2 2 2
High 1 1 1
Low 1.5
†
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
This data sheet limit may vary among suppliers.
PLZ
= 50 pF (unless otherwise noted) (see Figures 1 and 2)
L
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
†
1.2
1.5
1.7
1.9
2.1
1.9
2.4
1.5
3.8 5.2 1.2
†
3.4 6.3 1.5
†
4.4 5.6 1.7
†
4.1 6.3 1.3
2.2 5 6.2 2.2 8.3 2.2 7.4
†
4.1 6.5 2.1
†
2
4.4 6.3 2
†
4.5 6.8 1.9
1 3.4 4.5
2 4.3 5.7
†
4.9 6.2 2.4
†
4.2 6.3 1.5
SN54ABT843 SN74ABT843
†
2.3
SN54ABT843 SN74ABT843
†
†
†
†
†
†
†
†
1 6.4 1 5.7
†
2 6.6 2 6.5
†
†
1.5
7.8 1.2†6.7
7.3 1.5
8.3 1.7†7.2
7.2 1.9
7.5 2.1
7.6 2
8.1 1.9
7.3 2.4
7 1.5†5.9
UNIT
ns
†
UNIT
†
†
7.2
†
†
6.9
†
7.2
†
7.1
†
8
†
†
6.8
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
recovery-time waveform
PRE, CLR
LE
t
PLH
Q
Q
t
PHL
Figure 1. CLR and PRE Pulse Duration, CLR and PRE to Output Delay,
and CLR and PRE to Latch-Enable Recovery Time
1.5 V 1.5 V
t
w(L)
1.5 V
1.5 V
t
REC
1.5 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 2. Load Circuit and Voltage Waveforms
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7
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