Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
description
The ’ABT843 9-bit latches are designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The nine transparent D-type latches provide true
data at the outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are also in the
high-impedance state during power-up and
power-down conditions. The outputs remain in the
high-impedance state while the device is powered
down. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
SN54ABT843 . . . JT OR W PACKAGE
SN74ABT843 . . . DB, DW, OR NT P ACKAGE
SN54ABT843 . . . FK PACKAGE
3D
4D
5D
NC
6D
7D
8D
NC – No internal connection
(TOP VIEW)
1
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
(TOP VIEW)
2D1DOE
426
3212827
5
6
7
8
9
10
11
12 13
9D
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CC
NC
V
14 15 16 17 18
LE
NC
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
1Q
PRE
2Q
25
24
23
22
21
20
19
9Q
3Q
4Q
5Q
NC
6Q
7Q
8Q
OE
does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT843 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT843 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
FUNCTION TABLE
INPUTS
PRECLROELED
LXLXXH
HLLXX L
HHLHL L
HHLHH H
HHLLX Q
XXHXXZ
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
†
OE
PRE
CLR
LE
1D
2D
3D
4D
5D
6D
7D
8D
9D
1
14
11
13
2
3
4
5
6
7
8
9
10
EN
S2
R
C1
1D
2
23
22
21
20
19
18
17
16
15
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
OE
14
PRE
11
CLR
13
LE
2
1D
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
9-BIT BUS-INTERFACE D-TYPE LATCHES
S2
C1
1D
R
To Eight Other Channels
SN54ABT843, SN74ABT843
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
23
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 and 2)
VCC = 5 V,
TA = 25°C
MINMAXMINMAXMINMAX
CLR low5.55.55.5
t
w
†
This data sheet limit may vary among suppliers.
Pulse duration
p
PRE
low4.54.54.5
LE low3.33.33.4
Low2.52.52.5
High333
PRE inactive1.61.61.6
CLR inactive222
High111
Low1.5
†
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
This data sheet limit may vary among suppliers.
PLZ
= 50 pF (unless otherwise noted) (see Figures 1 and 2)
L
FROM
TO
VCC = 5 V,
TA = 25°C
MINTYPMAXMINMAXMINMAX
†
1.2
1.5
1.7
1.9
2.1
1.9
2.4
1.5
3.85.21.2
†
3.46.31.5
†
4.45.61.7
†
4.16.31.3
2.256.22.28.32.27.4
†
4.16.52.1
†
2
4.46.32
†
4.56.81.9
13.44.5
24.35.7
†
4.96.22.4
†
4.26.31.5
SN54ABT843SN74ABT843
†
2.3
SN54ABT843SN74ABT843
†
†
†
†
†
†
†
†
16.415.7
†
26.626.5
†
†
1.5
7.81.2†6.7
7.31.5
8.31.7†7.2
7.21.9
7.52.1
7.62
8.11.9
7.32.4
71.5†5.9
UNIT
ns
†
UNIT
†
†
7.2
†
†
6.9
†
7.2
†
7.1
†
8
†
†
6.8
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
recovery-time waveform
PRE, CLR
LE
t
PLH
Q
Q
t
PHL
Figure 1. CLR and PRE Pulse Duration, CLR and PRE to Output Delay,
and CLR and PRE to Latch-Enable Recovery Time
1.5 V1.5 V
t
w(L)
1.5 V
1.5 V
t
REC
1.5 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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