Datasheet SN74ABT827DBLE, SN74ABT827DBR, SN74ABT827DW, SN74ABT827DWR, SN74ABT827NT Datasheet (Texas Instruments)

SN54ABT827, SN74ABT827

10-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS159D – JANUARY 1991 – REVISED MA Y 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs

description

These 10-bit buffers or bus drivers provide a
high-performance bus interface for wide data
paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all ten outputs are in
the high-impedance state. The ’ABT827 provide
true data at the outputs.

When VCC is between 0 and 2.1 V, the device
is in the high-impedance state during power up
or power down. However, to ensure
the high-impedance state above 2.1 V, OE
be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by
the current-sinking capability of the driver.

should

SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE

SN54ABT827 . . . JT PACKAGE

(TOP VIEW)

1

OE1

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

A9

11

A10

GND

SN54ABT827 . . . FK PACKAGE

A3
A4
A5

NC

A6
A7
A8

NC – No internal connection

12

(TOP VIEW)

A2A1OE1NCY1

3212827

426

5
6
7
8
9
10
11

12 13

14 15 16 1718

A9

A10

GND

24
23
22
21
20
19
18
17
16
15
14
13

NC

CC

V

OE2

V

CC

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2

Y10

Y2

25
24
23
22
21
20
19

Y9

Y3
Y4
Y5
NC
Y6
Y7
Y8

The SN54ABT827 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT827 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

OE1 OE2 A

L L L L

L LH H
H XX Z
X H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

INPUTS

OUTPUT

Y

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT827, SN74ABT827

†

10-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS159D – JANUARY 1991 – REVISED MA Y 1997

logic symbol

1

OE1

13

OE2

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

A9

11

A10

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, and PW packages.

&

EN

1

23
22
21
20
19
18
17
16
15
14

logic diagram (positive logic)

1

OE1

13

OE2

223

A1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10

Y1

To Nine Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT827 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT827 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54ABT827, SN74ABT827

10-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS159D – JANUARY 1991 – REVISED MA Y 1997

recommended operating conditions (see Note 3)

SN54ABT827 SN74ABT827

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 5 5 ns/V
∆t/∆V

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

CC

0 V

CC

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT827, SN74ABT827

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

V

V

V

V

V

I

V

CC

GND

V

CC

CC

(INPUT)

(OUTPUT)

A

Y

ns

OE

Y

ns

OE

Y

ns

10-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS159D – JANUARY 1991 – REVISED MA Y 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT827 SN74ABT827

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

OL

V

hys

I

I

I

OZPU

I

OZPD

I

OZH

I

OZL

I

off

I

CEX

¶

I

O

I

CC

∆I

CC

C

i

C

o

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

This data sheet limit may vary among suppliers.

¶

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

#

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA

‡

VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±10 ±50 µA

‡

VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±10 ±50 µA
VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10
VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –140 –225

VCC = 5.5 V, IO = 0,

=

or

=

#

= 5.5 V,
One input at 3.4 V ,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 4 pF
VO = 2.5 V or 0.5 V 8 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

§

§

§

–50 –225
Outputs high 80 250 250 250 µA
Outputs low 35 40
Outputs disabled 80 250 250 250 µA
Outputs enabled 1.5 1.5 1.5 mA
Outputs disabled 50 50 50 µA
Control inputs 1.5 1.5 1.5 mA

§

10 10

–10 –10

§

–50 –225

§

40

40

§

µA

§

µA

§

mA

§

mA

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

§

4

PLZ

This data sheet limit may vary among suppliers.

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

TO

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

1.1 2.6 4.4 1.1 4.9 1.1 4.8

1.1 2.3 4.1 1.1 4.8 1.1 4.7

§

1

3.2 5.1 1 6 1

§

1

3.3 5.9 1 7.1 1

2 4.9 6.3 2 7 2 6.8

§

1.3

4.2 6.6 1.3 7.9 1.3

SN54ABT827 SN74ABT827

§

5.9

§

6.9

§

6.9

UNIT

SN54ABT827, SN74ABT827

10-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS159D – JANUARY 1991 – REVISED MA Y 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

1.5 V1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated