Texas Instruments SN74ABT7820-15PH, SN74ABT7820-15PN, SN74ABT7820-20PH, SN74ABT7820-20PN, SN74ABT7820-25PH Datasheet
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SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Advanced BiCMOS Technology
D
Independent Asynchronous Inputs and
Outputs
D
Two Separate 512 × 18 FIFOs Buffering
Data in Opposite Directions
D
Programmable Almost-Full/Almost-Empty
Flags
D
Empty, Full, and Half-Full Flags
D
Fast Access Times of 12 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
D
Supports Clock Rates up to 67 MHz
D
Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
GBA
SBA
GND
LDCKA
UNCKB
EMPTYB
EMPTYA
UNCKA
LDCKB
GND
SAB
GAB
A12
A13
A14
V
CC
V
CC
A15
GND
GND
A16
A17
B17
B16
B15
B14
B13
B12
24
65
4025
41
641
RSTA
PENA
AF/AEA
HFA
FULLA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
A11
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
26 27 28 29 30 3132 33 34 3536 37 38 39
8079 78 77 76 75 74 73 72 7170 69 68 6766
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
PH PACKAGE
(TOP VIEW)
RSTB
PENB
AF/AEB
HFB
FULLB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
B1 1
GND
CC
VCCVCCVCCV
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A11
GND
V
CC
A17
B11
A12
A13
GND
A14
A15
A16
B17
B16
GND
B15
B14
B13
B12
GND
PENB
SAB
GND
UNCKA
EMPTYA
EMPTYB
UNCKB
SBA
GBA
PENA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25
60
59
58
57
56
55
54
53
52
51
50
48
49
47
46
45
44
43
42
41
4026 27 28 29 30 31 32 33 34 35 36 37 38 39
80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 6172
V
CC
PN PACKAGE
(TOP VIEW)
RSTB
GAB
LDCKB
LDCKA
GND
RSTA
AF/AEA
HFA
FULLA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
AF/AEB
HFB
FULLB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
CC
VCCVCCVCCV
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It
processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from 0°C to 70°C.
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
SABLSBAXGABHGBA
L
FIFO A
In Out
FIFO B
Out In
Bus A
Bus B
SABXSBALGABLGBA
H
SABHSBAXGABHGBA
L
SABXSBAHGABLGBA
H
SABXSBAXGABLGBA
L
SABHSBALGABHGBA
H
SABLSBAHGABHGBA
H
SABHSBAHGABHGBA
H
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
FIFO A
Bus A
In
Bus B
Out
FIFO B
Out In
FIFO A
In Out
FIFO B
Out In
Bus A
Bus B
Figure 1. Bus-Management Functions
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SELECT-MODE CONTROL TABLE
CONTROL
OPERATION
SBA SAB A BUS B BUS
L L Real-time B-to-A bus Real-time A-to-B bus
H L FIFO B-to-A bus Real-time A-to-B bus
L H Real-time B-to-A bus FIFO A-to-B bus
H H FIFO B-to-A bus FIFO A-to-B bus
OUTPUT-ENABLE CONTROL TABLE
CONTROL
OPERATION
GBA GAB A BUS B BUS
L L Isolation/input to A bus Isolation/input to B bus
H L A bus enabled Isolation/input to B bus
L H Isolation/input to A bus B bus enabled
H H A bus enabled B bus enabled
Figure 1. Bus-Management Functions (Continued)
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
69
UNCKA
LDCKA
A1
63
PROG ENB
75
EMPTYB
PROG ENA
2
EMPTYA
70
FULLA
5
77
LDCKA
UNCKA
RESET A
1
EN2
80
GBA
EN1
65
GAB
0
79
SBA
1
66
SAB
60
FULLB
UNCKB
76
LDCKB
68
64
RESET B
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
57
55
54
52
51
49
48
8
10
11
13
14
16
17
A8
19
B8
46
ALMOST FULL/
3
AF/AEA
ALMOST EMPTY A
AF/AEB
62
ALMOST FULL/
ALMOST EMPTY B
0
7
A0
B0
58
0
HALF-FULL A
4
HFA HFB
61
HALF-FULL B
A10
A11
A12
A13
A14
A15
A16
22
23
25
26
28
29
31
A17
32
20
A9
B10
B11
B12
B13
B14
B15
B16
43
42
40
39
37
36
34
B17
33
B9
45
A Data B Data
LDCKB
UNCKB
Φ
FIFO
512 × 18 × 2
SN74ABT7820
MODE
17
17
RSTA
PENA
FULLA
EMPTYA
RSTB
PENB
FULLB
EMPTYB
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.
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