Datasheet SN74ABT652DBLE, SN74ABT652DBR, SN74ABT652DW, SN74ABT652DWR, SN74ABT652NT Datasheet (Texas Instruments)

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

Copyright  1994, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

• ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)

• Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

• T ypical V

OLP

(Output Ground Bounce)

< 1 V at V

CC

= 5 V, TA = 25°C

• High-Drive Outputs (–32-mA I

OH

,

64-mA IOL)

• Package Options Include Plastic

Small-Outline ((DW)) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs

description

These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.

Output-enable (OEAB and OEBA

) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the ′ABT652.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA

. In this configuration, each output reinforces its input. When all other

data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a

pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).

The SN74ABT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

CLKAB

SAB

OEAB

A1
A2
A3
A4
A5
A6
A7
A8

GND

V

CC

CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8

SN54ABT652 ...JT PACKAGE

SN74ABT652 ... DB, DW, OR NT PACKAGE

(TOP VIEW)

OEAB

321

13 14

5
6
7
8
9
10
11

OEBA
B1
B2
NC
B3
B4
B5

A1
A2
A3

NC

A4
A5
A6

4

15 16 17 18

A8

GND

NC

B8B7B6

SAB

CLKAB

NC

SN54ABT652 . . . FK PACKAGE

(TOP VIEW)

28 27 26

25
24
23
22
21
20
19

12

A7

V

CLKBA

SBA

NC – No internal connection

CC

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN54ABT652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT652 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/O

†

OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8

OPERATION OR FUNCTION

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data

X H ↑ H or L X X Input Unspecified

‡

Store A, hold B

H H ↑↑X

‡

X Input Output Store A in both registers

L X H or L ↑ X X Unspecified

‡

Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

Stored A data to B bus and

stored B data to A bus

†

The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

3

X
L
L

OEAB

3

L

21

L

1

CLKAB

X

23

CLKBA

X

2

SAB

X

22

SBA

L

1

CLKAB

X

23

CLKBA

X

2

SAB

L

22

SBA

X

21

H

1

CLKAB23CLKBA

X

2

SAB

X

22

SBA

X

1

CLKAB23CLKBA2SAB22SBA

X
H

XX

X

X
X

HL L HH

↑

↑
↑↑

OEBA

OEBA

3

H

21

H

OEAB OEBA

321

OEAB OEBA

L

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

Figure 1. Bus-Management Functions

Pin numbers shown are for the DB, DW, JT, and NT packages.

SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

OEBA

EN1 [BA]

21

G5

22

SBA

A1

4

B1

20

4D

EN2 [AB]

3

OEAB

23

CLKBA

1

CLKAB

G7

2

SAB

5

7

7

5

1

1

6D ≥1

≥1

1

2

C6

C4

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, and NT packages.

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

A1

B1

1D

C1

1D

C1

One of Eight

Channels

20

4

2

1

22

23

21

3

SAB

CLKAB

SBA

CLKBA

OEAB

OEBA

To Seven Other Channels

Pin numbers shown are for the DB, DW, JT, and NT packages.

SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT652 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT652 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.65 W. . . . . . . . . . . . . . . . . . .

DW package 1.7 W. . . . . . . . . . . . . . . . . . .

NT package 1.3 W. . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero. For more information, refer to the

Package Thermal Considerations

application note in the 1994

ABT Advanced BiCMOS T echnology Data Book

, literature number SCBD002B.

recommended operating conditions (see Note 3)

SN54ABT652 SN74ABT652

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate 5 5 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused or floating pins (input or I/O) must be held high or low.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT652 SN74ABT652

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

V

OH

IOH = –24 mA 2 2

V

V

CC

=

4.5 V

IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55

VOLV

CC

= 4.5

V

IOL = 64 mA 0.55* 0.55

V

V

= 5.5 V,

Control inputs ±1 ±1 ±1

I

I

CC

,

VI = VCC or GND

A or B ports ±100 ±100 ±100

µ

A

I

OZH

‡

VCC = 5.5 V, VO = 2.7 V 50 50 50 µA

I

OZL

‡

VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA

I

O

§

VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

Outputs high 250 250 250 µA

I

CC

VCC = 5.5 V, IO = 0,

Outputs low 30 30 30 mA

V

I

=

V

CC

or

GND

Outputs disabled 250 250 250 µA

∆I

CC

¶

VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND

1.5 1.5 1.5 mA

C

i

VI = 2.5 V or 0.5 V Control inputs 7 pF

C

io

VO = 2.5 V or 0.5 V A or B ports 12 pF

* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

The parameters I

OZH

and I

OZL

include the input leakage current.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)

VCC = 5 V,

TA = 25°C

SN54ABT652 SN74ABT652

UNIT

MIN MAX MIN MAX MIN MAX

f

clock

Clock frequency 0 125 0 125 0 125 MHz

t

w

Pulse duration, CLK high or low 4 4 4 ns

t

su

Setup time, A or B before CLKAB↑ or CLKBA↑ 3.5 3.5 3.5 ns

t

h

Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 0 ns

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 2)

PARAMETER

FROM

TO

VCC = 5 V,

TA = 25°C

SN54ABT652 SN74ABT652

UNIT

(INPUT)

(OUTPUT)

MIN TYP MIN MIN MAX MIN MAX

f

max

125 200 125 125 MHz

t

PLH

2.2 5.3 6.8 2.2 8.2 2.2 7.8

t

PHL

CLK

B or A

1.7 5.9 7.4 1.7 8.8 1.7 8.4

ns

t

PLH

1.5 4.4 5.7 1.5 7 1.5 6.7

t

PHL

A or B

B or A

1.5 4.4 5.7 1.5 7 1.5 6.7

ns

t

PLH

1.5 4.6 5.9 1.5 7.4 1.5 6.9

t

PHL

SAB

or

SBA

†

B or A

1.5 5.4 6.7 1.5 8 1.5 7.7

ns

t

PZH

1.3 3.3 4.6 1.3 6 1.3 5.8

t

PZL

OEBA

A

2.5 4.5 6.8 2.5 8.9 2.5 8.5

ns

t

PHZ

1.5 6.2 7.7 1.5 8.3 1.5 8.2

t

PLZ

OEBA

A

1.5 5 6.3 1.5 7.1 1.5 6.8

ns

t

PZH

1.8 3.8 6.1 1.8 6.9 1.8 6.5

t

PZL

OEAB

B

2.9 4.9 6.5 2.9 7.6 2.9 7.4

ns

t

PHZ

1.5 4.5 5.7 1.5 7.1 1.5 6.9

t

PLZ

OEAB

B

1.5 4.1 5.3 1.5 6.6 1.5 6.2

ns

†

These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

7 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V 1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

(see Note B)

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note C)

Output

Waveform 2

S1 at Open

(see Note C)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

Output

Control

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS070D – JULY 1991 – REVISED JULY 1994

2–10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1998, Texas Instruments Incorporated