Datasheet SN74ABT574AN, SN74ABT574APWLE, SN74ABT574APWR, SN74ABT574ADBLE, SN74ABT574ADBR Datasheet (Texas Instruments)
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SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the SN54ABT574 and
SN74ABT574A are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the Q outputs are set to the logic
levels set up at the data (D) inputs.
SN54ABT574 ...J OR W PACKAGE
SN74ABT574A . . . DB, DW, N, OR PW PACKAGE
SN54ABT574 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
9
8D
GND
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
GND
20
19
18
17
16
15
14
13
12
11
CLK
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
18
17
16
15
14
7Q 1Q
CC
2Q
3Q
4Q
5Q
6Q
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT574A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1D
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
19
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT574 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT574A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT574 SN74ABT574A
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
0 V
CC
V
†
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3
SN54ABT574, SN74ABT574A
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
V
V
V
V
V
I
V
CC
GND
t
Set
CLK↑
ns
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT574 SN74ABT574A
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
OL
V
hys
I
I
I
OZH
I
OZL
I
off
I
CEX
§
I
O
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This data sheet limit may vary among suppliers.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA
VCC = 5 V, IOH = –3 mA
or
IOH = –24 mA
IOH = –32 mA
IOL = 48 mA
IOL = 64 mA
Outputs high
Outputs low
Outputs disabled
=
CC
= 4.5
CC
VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±500 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
VCC = 5.5 V, One input at 3.4 V,
¶
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 6.5 pF
2.5 2.5 2.5
3 3 3
2 2
2* 2
0.55 0.55
0.55* 0.55
100 mV
‡
‡
1 250 250 250
24 30 30 30
0.5 250 250 250
1.5 1.5 1.5 mA
10
–10
‡
‡
10
–10
‡
µA
‡
µA
µA
mA
µA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT574
4
f
clock
t
w
su
t
h
Clock frequency 150 150 MHz
Pulse duration, CLK high or low 3.3 3.3 ns
Hold time, data after CLK↑ High or low 2 2 ns
p
up time, data before
High 1.5 1.5
Low 2 2
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VCC = 5 V,
TA = 25°C
MIN MAX
MIN MAX
UNIT
t
Set
CLK↑
ns
CLK
Q
ns
OE
Q
ns
OE
Q
ns
CLK
Q
ns
OE
Q
ns
OE
Q
ns
SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT574A
VCC = 5 V,
f
clock
t
w
su
t
h
†
This data sheet limit may vary among suppliers.
Clock frequency 150 150 MHz
Pulse duration, CLK high or low 3.3 3.3 ns
p
up time, data before
Hold time, data after CLK↑ High or low 1.8
TA = 25°C
MIN MAX
High 1 1
Low 1.5 1.5
†
MIN MAX
†
1.8
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
SN54ABT574
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 200 150 MHz
2.2 3.9 6.2 2.2 7
3 4.8 7 3 7.4
1 3.3 5 1 5.8
2.5 4.7 5.9 2.5 7.2
2.4 4.9 6.2 2.4 7.2
2 4 5.8 2 6.9
MIN MAX
UNIT
ns
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
†
This data sheet limit may vary among suppliers.
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
SN74ABT574A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 200 150 MHz
2.2 3.9 6.2 2.2 6.8
3 4.8 6.6 3 7.1
1 3.3 4.3 1 5.1
†
2.1
2.4 4.9 6.2 2.4 7
4.7 5.9 2.1
2 4 5.8 2 6.5
MIN MAX
†
UNIT
6.7
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5
SN54ABT574, SN74ABT574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS191C – JANUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
6
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