Datasheet SN74ABT534AN, SN74ABT534APWLE, SN74ABT534APWR, SN74ABT534ADBLE, SN74ABT534ADBR Datasheet (Texas Instruments)

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package

description

These 8-bit flip-flops with 3-state outputs are
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK), the Q

outputs are set to the complement of

the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.

OE does not affect the internal operations of the flip-flop. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT534 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT534A is characterized for operation from –40°C to 85°C.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

OE

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

SN54ABT534 ...J OR W PACKAGE

SN74ABT534A . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

3212019

9

10 11 12 13

4
5
6
7
8

18
17
16
15
14

8D
7D
7Q
6Q
6D

2D
2Q
3Q
3D
4D

SN54ABT534 . . . FK PACKAGE

(TOP VIEW)

1D1QOE

5Q

5D

8Q

4Q

GND

CLK

V

CC

SN54ABT534, SN74ABT534A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE CLK D

Q

L ↑ H L
L ↑ LH
L H or L X Q

0

H X X Z

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

1D

3

1D

4

2D

7

3D

8

4D

13

5D

14

6D

17

7D

18

8D

2
5
6

9
12
15
16
19

EN

1

C1

11

CLK

OE

1Q
2Q

3Q
4Q
5Q
6Q

8Q

7Q

logic diagram (positive logic)

1D

C1

OE

1D

1Q

CLK

1

11

3

2

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I

O

: SN54ABT534 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT534A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ABT534 SN74ABT534A

MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT534 SN74ABT534A

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA

2.5 2.5 2.5

VCC = 5 V, IOH = –3 mA

3 3 3

V

OH

IOH = –24 mA

2 2

V

V

CC

= 4.5

V

IOH = –32 mA

2* 2

IOL = 48 mA

0.55 0.55

V

OL

V

CC

=

4.5 V

IOL = 64 mA

0.55* 0.55

V

V

hys

100 mV

I

I

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA

I

OZH

VCC = 5.5 V, VO = 2.7 V 10

‡

10

‡

10

‡

µA

I

OZL

VCC = 5.5 V, VO = 0.5 V –10

‡

–10

‡

–10

‡

µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA

I

O

§

VCC = 5.5 V, VO = 2.5 V –50 –100 –180

‡

–50 –180

‡

–50 –180

‡

mA

Outputs high

1 250 250 250

µA

I

CC

VCC = 5.5 V, IO = 0,

Outputs low

24 30 30 30

mA

V

I

=

V

CC

or

GND

Outputs disabled

0.5 250 250 250

µA

∆I

CC

¶

VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND

1.5 1.5 1.5 mA

C

i

VI = 2.5 V or 0.5 V 3.5 pF

C

o

VO = 2.5 V or 0.5 V 6.5 pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This data sheet limit may vary among suppliers.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

SN54ABT534, SN74ABT534A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN54ABT534

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN MAX

f

clock

Clock frequency 125 125 MHz

t

w

Pulse duration CLK high or low 3.5 3.5 ns

t

su

Setup time, data before CLK↑

High or low 1.6 1.6 ns

t

h

Hold time, data after CLK↑ High or low 1.6 1.6 ns

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN74ABT534A

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN MAX

f

clock

Clock frequency 125 125 MHz

t

w

Pulse duration CLK high or low 3.5 3.5 ns

t

su

Setup time, data before CLK↑

High or low 1.6 1.6 ns

t

h

Hold time, data after CLK↑ High or low 2

†

2

†

ns

†

This data sheet limit may vary among suppliers.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN54ABT534

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,
TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

f

max

125 175 125 MHz

t

PLH

2.6 4.5 6.1 2.6 7

t

PHL

CLK

Q

3.4 5.5 6.7 3.4 7.9

ns

t

PZH

1 3.4 5.2 1 5.8

t

PZL

OE

Q

2.6 4 5.8 2.6 7

ns

t

PHZ

2.4 4.7 6.6 2.4 7.6

t

PLZ

OE

Q

2.3 3.8 5.8 2.3 6.8

ns

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN74ABT534A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

f

max

125 175 125 MHz

t

PLH

2.6 4.5 5.9 2.6 6.7

t

PHL

CLK

Q

3.4 5.5 6.7 3.4 7.6

ns

t

PZH

1 3.4 4.2 1 5

t

PZL

OE

Q

2.6 4 5.8 2.6 6.8

ns

t

PHZ

2.4 4.7 6.6 2.4 7.3

t

PLZ

OE

Q

2.3 3.8 5.8 2.3 6.5

ns

SN54ABT534, SN74ABT534A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

Output

Control

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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Copyright  1998, Texas Instruments Incorporated