Datasheet SN74ABT377ADBLE, SN74ABT377ADBR, SN74ABT377ADW, SN74ABT377ADWR, SN74ABT377AN Datasheet (Texas Instruments)

SN54ABT377, SN74ABT377A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package

description

These 8-bit positive-edge-triggered D-type
flip-flops with a clock (CLK) input are particularly
suitable for implementing buffer and storage
registers, shift registers, and pattern generators.

Data (D) input information that meets the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse if the
common clock-enable (CLKEN

) input is low.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive-going pulse. When the
buffered clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output. The circuits are designed to prevent false
clocking by transitions at CLKEN

.
The SN54ABT377 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT377A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLKEN CLK D

Q

H X X Q

0

L ↑ HH
L ↑ LL
X H or L X Q

0

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

SN54ABT377 ...J OR W PACKAGE

SN74ABT377A . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

SN54ABT377 . . . FK PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

CLKEN

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

3 2 1 20 19

9 10 11 12 13

4
5
6
7
8

18
17
16
15
14

2D
2Q
3Q
3D
4D

1D1QCLKEN

5Q

5D

8Q

4Q

GND

CLK

V

CC

8D
7D
7Q
6Q
6D

SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

2D

3

1D

4

2D

7

3D

G1

1

1Q

2

2Q

5

3Q

6

8

4D

13

5D

14

6D

4Q

9

5Q

12

6Q

15

CLKEN

17

7D

18

8D

11

CLK

7Q

16

8Q

19

1C2

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1D

1Q

1D

C1

CLK

CLKEN

To Seven Other Channels

11

1

3

2

SN54ABT377, SN74ABT377A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT377 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT377A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

recommended operating conditions (see Note 3)

SN54ABT377 SN74ABT377A

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT377 SN74ABT377A

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA

2.5 2.5 2.5

VCC = 5 V, IOH = –3 mA

3 3 3

V

OH

IOH = –24 mA

2 2

V

V

CC

=

4.5 V

IOH = –32 mA

2* 2

IOL = 48 mA

0.55 0.55

V

OL

V

CC

= 4.5

V

IOL = 64 mA

0.55* 0.55

V

V

hys

100 mV

I

I

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA

I

O

‡

VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
V

= 5.5 V, I

= 0,

Outputs high

1 250 250 250

µA

I

CC

CC

,

O

,

VI = VCC or GND

Outputs low

24 30 30 30

mA

∆I

CC

§

VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND

1.5 1.5 1.5 mA

C

i

VI = 2.5 V or 0.5 V 3.5 pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN54ABT377

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN MAX

f

clock

Clock frequency 0 150 0 150 MHz

t

w

Pulse duration CLK high or low 3.3 3.3 ns

p

Data high or low 2 2.5

t

su

Setup time before CLK↑

CLKEN high or low 3 3

ns

Data high or low 1.8

¶

1.8

¶

t

h

Hold ti

me after

CLK↑

CLKEN high or low 1.8

¶

1.8

¶

ns

¶

This data sheet limit may vary among suppliers.

SN54ABT377, SN74ABT377A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN74ABT377A

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN MAX

f

clock

Clock frequency 0 150 0 150 MHz
t

w

Pulse duration CLK high or low 3.3 3.3 ns

p

Data high or low 2 2.5

t

su

Setup time before CLK↑

CLKEN high or low 3 3

ns

Data high or low 1.8

†

1.8

†

t

h

Hold ti

me after

CLK↑

CLKEN high or low 1.2

†

1.2

†

ns

†

This data sheet limit may vary among suppliers.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN54ABT377

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

f

max

150 150 MHz

t

PLH

2.2 4.5 6 2.2 7

t

PHL

CLK

Q

3.1 5.3 6.8 2 7.6

ns

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN74ABT377A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

f

max

150 150 MHz

t

PLH

2.2 4.5 6 2.2 6.5

t

PHL

CLK

Q

2.6

†

5.3 6.8 2.6

†

7.3

ns

†

This data sheet limit may vary among suppliers.

SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE

SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

Output

Control

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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