Texas Instruments SN74ABT3614-15PCB, SN74ABT3614-15PQ, SN74ABT3614-20PCB, SN74ABT3614-20PQ, SN74ABT3614-30PCB Datasheet
...
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
Two Independent 64 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
D
Mailbox-Bypass Register for Each FIFO
D
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
D
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
D
Three Modes of Byte-Order Swapping on
Port B
D
Programmable Almost-Full and
Almost-Empty Flags
D
Microprocessor Interface Control Logic
D
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
D
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
D
Passive Parity Checking on Each Port
D
Parity Generation Can Be Selected for Each
Port
D
Low-Power Advanced BiCMOS Technology
D
Supports Clock Frequencies up to 67 MHz
D
Fast Access Times of 10 ns
D
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
description
The SN74ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory . It supports clock
frequencies up to 67 MHz and has read-access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected number of
words is stored in memory . FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with
a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any
bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN74ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array . The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN74ABT3614 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
•
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications
(literature
number SCAA014)
•
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
•
Internetworking the SN74ABT3614
(literature number SCAA015)
•
Metastability Performance of Clocked FIFOs
(literature number SCZA004)
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
91
92
60
30
61
A24
A25
A26
A27
A28
GND
A30
A31
A32
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
B26
B25
B24
B23
AFA
FFA
CSA
CLKA
W/RA
PEFA
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
SW1
SW0
SIZ0
MBF1
PEFB
PGB
W/RB
CLKB
ENB
CSB
CC
V
CC
V
CC
V
BE
PCB PACKAGE
(TOP VIEW)
A33
CC
V
FFB
SIZ1
PGA
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
V
CC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
AFB
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
V
CC
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
A29
ENA
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
5251 83828180797877767574737271706968676665646362616059585756555453
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
V
CC
A7
A8
A9
GND
A10
A11
V
CC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
V
CC
B7
B8
B9
GND
B10
B11
V
CC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
PQ PACKAGE
†
(TOP VIEW)
AFA
FFAVENA
CLKA
W/RA
PGA
PEFA
GND
MBF2
MBA
FS0
ODD/EVEN
RST
GNDBESW1
SW0
SIZ1
SIZ0
MBF1
GND
PGB
W/RB
CLKB
ENB
CSB
FFB
AFB
A24
A25
A26
GND
A27
A29
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
GND
B32
B31
B30
B29
B28
B27
GND
B26
B25
B24
CC
A28
B33
CC
V
CSA
FS1
PEFB
CC
V
V
CC
CC
V
CC
V
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Port-A
Control
Logic
AFA
FIFO1
Programmable-Flag
Offset Register
Read
Pointer
64 × 36
SRAM
Port-B
Control
Logic
BE
Parity
Gen/Check
Write
Pointer
Mail2
Register
FIFO2
Status-Flag
Logic
Status-Flag
Logic
Write
Pointer
CLKA
CSA
W/RA
ENA
MBA
FFA
FS0
A0–A35
EFA
AEA
Device
Control
64 × 36
SRAM
Output Register
Mail1
Register
Read
Pointer
Input Register
Output Register
FS1
MBF2
AEB
CLKB
CSB
ENB
36
36
RST
MBF1
EFB
B0–B35
FFB
AFB
PEFB
PGB
ODD/
EVEN
Input Register
W/RB
Parity
Gen/Check
PEFA
PGA
Parity
Generation
Parity
Generation
SIZ0
SIZ1
SW0
SW1
Bus Matching and
Byte Swapping
Bus Matching and
Byte Swapping
36
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O DESCRIPTION
A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
AEA
O
(port A)
Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words
in FIFO2 is less than or equal to the value in offset register X.
AEB
O
(port B)
Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words
in FIFO1 is less than or equal to the value in offset register X.
AFA
O
(port A)
Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty
locations in FIFO1 is less than or equal to the value in offset register X.
AFB
O
(port B)
Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty
locations in FIFO2 is less than or equal to the value in offset register X.
B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
BE I
Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the
most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.
CLKA I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. EFA
, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA.
CLKB I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-to-high
transition of CLKB. EFB
, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB.
CSA I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA
is high.
CSB I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB
is high.
EFA
O
(port A)
Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and
reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA
is high. EFA is forced
low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty
FIFO2 memory.
EFB
O
(port B)
Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and
reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB
is high. EFB is
forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded
into empty FIFO1 memory.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FFA
O
(port A)
Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes
to its memory are disabled. FFA
is forced low when the device is reset and is set high by the second low-to-high
transition of CLKA after reset.
FFB
O
(port B)
Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes
to its memory are disabled. FFB
is forced low when the device is reset and is set high by the second low-to-high
transition of CLKB after reset.
FS1, FS0 I
Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the AE
flag and AF flag offset.
MBA I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIFO2 output register data for output.
MBF1 O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites
to the mail1 register are inhibited while MBF1
is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and both SIZ1 and SIZ0 are high. MBF1
is set high when the device is reset.
MBF2 O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites
to the mail2 register are inhibited while MBF2
is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2
is set high when the device is reset.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O DESCRIPTION
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN
is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA
O
(port A)
Port-A parity-error flag. When any byte applied to terminals A0–A35 fails parity, PEF A is low . Bytes are organized as
A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of the ODD/EVEN
input.
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/R
A low, MBA high, and PGA
high, the PEFA
flag is forced high, regardless of the state of the A0–A35 inputs.
PEFB
O
(port B)
Port-B parity-error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low . Bytes are organized
as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state
of the ODD/EVEN
input.
The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/R
B low, SIZ1 and SIZ0 high,
and PGB high, the PEFB
flag is forced high, regardless of the state of the B0–B35 inputs.
PGA I
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
is selected by the state of the ODD/EVEN
input. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGB I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of the ODD/EVEN
input. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.
The generated parity bits are output in the most-significant bit of each byte.
RST I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST
is low. This sets the AF A, AFB, MBF1, and MBF2 flags high and the EFA, EFB, AEA, AEB, FFA, and FFB
flags low. The low-to-high transition of RST latches the status of the FS1 and FS0 inputs to select AF flag and AE flag
offset.
SIZ0, SIZ1
I
(port B)
Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following
low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.
SW0, SW1
I
(port B)
Port-B byte-swap selects. At the beginning of each long word transfer, one of four modes of byte-order swapping is
selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
W/RA I
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R
A is high.
W/RB I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/R
B is high.
detailed description
reset
The SN74ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low , the almost-empty flags (AEA, AEB) low , and the almost-full flags (AF A, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of CLKA and FFB
is set high after two low-to-high transitions of CLKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
reset (continued)
T able 1. Flag Programming
FS1 FS0
RST
AF AND AE FLAG
OFFSET REGISTER (X)
H H ↑ 16
H L ↑ 12
L H ↑ 8
L L ↑ 4
FIFO write/read operation
The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA
is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA W/RA ENA MBA CLKA
A0–A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑ In high-impedance state FIFO1 write
L H H H ↑ In high-impedance state Mail1 write
L L L L X Active, FIFO2 output register None
L L H L ↑ Active, FIFO2 output register FIFO2 read
L L L H X Active, mail2 register None
L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)
The state of the port-B data (B0 –B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the
B0–B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of
CLKB when CSB
is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA
, CSB) and write/read
selects (W/R
A, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FIFO writer/read operation (continued)
Table 3. Port-B Enable Function Table
CSB W/RB ENB SIZ1, SIZ0 CLKB
B0–B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both low ↑ In high-impedance state FIFO2 write
L H H Both high ↑ In high-impedance state Mail2 write
L L L One, both low X Active, FIFO1 output register None
L L H One, both low ↑ Active, FIFO1 output register FIFO1 read
L L L Both high X Active, mail1 register None
L L H Both high ↑ Active, mail1 register Mail1 read (set MBF1 high)
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously
to one another. EF A, AEA, FFA, and AF A are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized
to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
NUMBER OF 36-BIT
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
WORDS IN FIFO1
†
EFB AEB AFA FFA
0 L L H H
1 to X H LHH
(X + 1) to [64 – (X + 1)] H HHH
(64 – X) to 63 H HLH
64 H H L L
†
X is the value in the AE flag and AF flag offset register.
Table 5. FIFO2 Flag Operation
NUMBER OF 36-BIT
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
WORDS IN FIFO2
†
EFA AEA AFB FFB
0 L L H H
1 to X H LHH
(X + 1) to [64 – (X + 1)] H HHH
(64 – X) to 63 H HLH
64 H H L L
†
X is the value in the AE flag and AF flag offset register.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
empty flags (EFA, EFB)
The FIFO empty flag is synchronized to the port clock that reads data from its array . When the empty flag is high,
new data can be read to the FIFO output register. When the empty flag is low , the FIFO is empty and attempted
FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when the fourth
byte or second word of the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written
to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty-flag synchronizing
clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register
and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was
written. The FIFO empty flag is set high by the second low-to-high transition of the synchronizing clock and the
new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time t
sk1
, or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 13 and 14).
full flags (FFA, FFB)
The FIFO full flag is synchronized to the port clock that writes data to its array. When the full flag is high, a
memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO,
the previous memory location is ready to be written in a minimum of three cycles of the full-flag synchronizing
clock. A full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next
memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after
the read sets the full flag high and data can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time t
sk1
, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The FIFO almost-empty flag is synchronized to the port clock that reads data from its array . The almost-empty
state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with
one of four preset values during a device reset (see
reset
). An AE flag is low when the FIFO contains X or fewer
long words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of the AE-flag synchronizing clock are required after a FIFO write for the AE flag to
reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more long words remains low
if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1)
level. An AE
flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write
that fills memory to the (X + 1) level. A low-to-high transition of an AE flag synchronizing clock begins the first
synchronization cycle if it occurs at time t
sk2
, or greater, after the write that fills the FIFO to (X + 1) long words.
Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 17 and
18).
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
almost-full flags (AFA, AFB)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array . The almost-full state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see
reset
). An almost-full flag is low when the FIFO contains (64 – X)
or more long words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.
Two low-to-high transitions of the AF
-flag synchronizing clock are required after a FIFO read for the AF flag to
reflect the new level of fill; therefore, the AF flag of a FIFO containing [64 – (X + 1)] or fewer words remains low
if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words
in memory to [64 – (X + 1)]. An AF flag is set high by the second low-to-high transition of the synchronizing clock
after the FIFO read that reduces the number of long words in memory to [64 – (X + 1)]. A low-to-high transition
of an AF
-flag synchronizing clock begins the first synchronization cycle if it occurs at time t
sk2
, or greater, after
the read that reduces the number of long words in memory to [64 – (X + 1)]. Otherwise, the subsequent
synchronizing clock cycle can be the first synchronization cycle (see Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB
writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low . Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (A0–A35) are active, the data on the bus comes from the FIFO2 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0–B35) are
active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are
low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1
) is set high
by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both SIZ1 and SIZ0 are
high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA,
W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only
when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1
or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big
endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to CLKB to communicate with peripherals of various bus widths.
The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are
stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next
rising edge on CLKB according to Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN74ABT3614.
Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2
RAM. Port-B bus sizing does not apply to mail-register operations.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dynamic bus sizing (continued)
Read From FIFO1/Write to FIFO2
Write to FIFO1/Read From FIFO2
(a) LONG WORD SIZE
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
(b) WORD SIZE – BIG ENDIAN
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
(c) WORD SIZE – LITTLE ENDIAN
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
3rd: Read From FIFO1/Write to FIFO2
4th: Read From FIFO1/Write to FIFO2
(d) BYTE SIZE – BIG ENDIAN
BYTE ORDER ON PORT A:
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
XLL
BE
SIZ1 SIZ0
ABCD
ABCD
AB
CD
CD
AB
A
B
C
D
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
LLH
BE SIZ1 SIZ0
HLH
BE
SIZ1 SIZ0
LHL
BE SIZ1 SIZ0
Figure 1. Dynamic Bus Sizing
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dynamic bus sizing (continued)
2nd: Read From FIFO1/Write to FIFO2
3rd: Read From FIFO1/Write to FIFO2
4th: Read From FIFO1/Write to FIFO2
(e) BYTE SIZE – LITTLE ENDIAN
1st: Read From FIFO1/Write to FIFO2
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
D
C
B
A
HHL
BE
SIZ1 SIZ0
Figure 1. Dynamic Bus Sizing (continued)
bus-matching FIFO1 reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIFO1 output register with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size
implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.
Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIFO1 in byte or word format, the unused B0–B35 outputs remain inactive but static
with the unused FIFO1 output register bits holding the last data value to decrease power consumption.
bus-matching FIFO2 writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes with a long-word bus size
immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write
before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port-B mail-register access
In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs
also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately. Any bus-sizing operation that is underway is unaffected by the mail-register access. After the
mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic
diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of
SIZ0_Q, SIZ1_Q, and BE
_Q.
MUX
CLKB
SIZ0
SIZ1
BE
SIZ0_Q
SIZ1_Q
BE
_Q
DQ
G1
1
1
Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register
byte swapping
The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous
to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads
a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first
word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is
transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIFO1 read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.
Loading...