Datasheet SN74ABT3613-20PCB, SN74ABT3613-20PQ, SN74ABT3613-30PCB, SN74ABT3613-30PQ, SN74ABT3613-15PCB Datasheet (Texas Instruments)

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SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low-Power Advanced BiCMOS Technology

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

64 × 36 FIFO Buffering Data From Port A to Port B

Mailbox-Bypass Registers in Each Direction

Dynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte)

Selection of Big- or Little-Endian Format for Word and Byte Bus Sizes

Three Modes of Byte-Order Swapping on Port B

Programmable Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

FF and AF Flags Synchronized by CLKA

EF and AE Flags Synchronized by CLKB

Passive Parity Checking on Each Port

Parity Generation Can Be Selected for Each Port

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 10 ns

Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Quad Flat (PQ) Packages

description

The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory . It supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO in this device buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory . FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses controlled by a synchronous interface.

The full flag (FF

) and almost-full (AF) flag of a FIFO are two-stage synchronized to the port clock that writes data

to its array . The empty flag (EF

) and almost-empty (AE) flag of a FIFO are two-stage synchronized to the port

clock that reads data from its array. The SN74ABT3613 is characterized for operation from 0°C to 70°C. For more information on this device family, see the following application reports:

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications

(literature number SCAA014)

Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications

(literature number SCAA015)

Internetworking the SN74ABT3614

(literature number SCAA018)

Metastability Performance of Clocked FIFOs

(literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

A24

A25

A26

A27

A28

GND

A30

A31

A32

A34

A35

GND

B35

B34

B33

B32

B31

B30

GND

B29

B28

B27

B26

B25

B24

B23

CSA

CLKA

W/RA

PEFA

MBF2

MBA

FS1

FS0

ODD/EVEN

RST

GND

SW1

SW0

SIZ0

MBF1

PEFB

PGB

W/RB

CLKB

ENB

CSB

PCB PACKAGE

(TOP VIEW)

A33

SIZ1

PGA

B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B1 1 B10 GND B9 B8 B7 V

B6 B5 B4 B3 GND B2 B1 B0 EF AE NC

A23 A22 A21

GND

A20 A19 A18 A17 A16 A15 A14 A13 A12 A1 1 A10

GND

A9 A8 A7

A6 A5 A4 A3

GND

A2 A1

A0 NC NC

A29

ENA

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GND

NC NC

A0 A1 A2

GND

A3 A4 A5 A6

A7 A8 A9

GND

A10 A11

A12 A13 A14

GND

A15 A16 A17 A18 A19 A20

GND

A21 A22 A23

GND AE EF B0 B1 B2 GND B3 B4 B5 B6 V

B7 B8 B9 GND B10 B11 V

B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23

PQ PACKAGE

†

(TOP VIEW)

FFVENA

CLKA

W/RA

PGA

PEFA

GND

MBF2

MBA

FS0

ODD/EVEN

RST

GNDBESW1

SW0

SIZ1

SIZ0

MBF1

GND

PGB

W/RB

CLKB

ENB

CSBNCNC

A24

A25

A26

GND

A27

A29

A30

A31

A32

GND

A33

A34

A35

GND

B35

B34

GND

B32

B31

B30

B29

B28

B27

GND

B26

B25

B24

A28

B33

CSA

FS1

PEFB

NC – No internal connection †

Uses Yamaichi socket IC51-1324-828

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

17 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118

131 129 127 125 123 121 119 117

51 52 53 54 55 56 5758 59 60 61 62 63 64 65 66 6768 70 72 74 76 78 80 8269 71 73 75 77 79 81 83

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Port-A

Control

Logic

FIFO

Programmable-Flag

Offset Register

Port-B

Control

Logic

Parity

Gen/Check

Mail2

Status-Flag

Logic

Write

Pointer

CLKA

CSA

W/RA

ENA

MBA

FS0

A0–A35

Device

Control

64 × 36

SRAM

Output Register

Mail1

Read

Pointer

FS1

MBF2

CLKB CSB

ENB

RST

MBF1

B0–B35

PEFB

PGB

ODD/

EVEN

Input Register

W/RB

Parity

Gen/Check

PEFA

PGA

Parity

Generation

SIZ0 SIZ1

SW0 SW1

Bus Matching and

Byte Swapping

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AE

(port B)

Almost-empty flag. Programmable almost-empty flag synchronized to CLKB. AE is low when the number of 36-bit words in the FIFO is less than or equal to the value in offset register X.

(port A)

Almost-full flag. Programmable almost-full flag synchronized to CLKA. AF is low when the number of 36-bit empty locations in the FIFO is less than or equal to the value in offset register X.

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B. BE

Big-endian select. Selects the bytes on port B used during byte or word FIFO reads. A low on BE selects the most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.

CLKA I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FF

and AF are synchronized to the low-to-high transition of CLKA.

CLKB I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-to-high transition of CLKB. EF

and AE are synchronized to the low-to-high transition of CLKB.

CSA

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0–A35 outputs are in the high-impedance state when CSA

is high.

CSB

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0–B35 outputs are in the high-impedance state when CSB

is high.

(port B)

Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads from its memory are disabled. Data can be read from the FIFO to the output register when EF

is high. EF is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO memory.

ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

(port A)

Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its memory are disabled. FF

is forced low when the device is reset and is set high by the second low-to-high transition

of CLKA after reset.

FS1 FS0

Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the AE

flag and AF flag offset.

MBA I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0–A35 outputs are active, mail2 register data is output.

MBF1

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites to the mail1 register are inhibited while MBF1

is low. MBF1 is set high by a low-to-high transition of CLKB when a

port-B read is selected and both SIZ1 and SIZ0 are high. MBF1

is set high when the device is reset.

MBF2

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites to the mail2 register are inhibited while MBF2

is low. MBF2 is set high by a low-to-high transition of CLKA when a

port-A read is selected and MBA is high. MBF2

is set high when the device is reset.

ODD/EVEN

Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when ODD/EVEN

is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled

for a read operation.

PEFA

(port A)

Port-A parity error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN

The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/R

A low, MBA high, and PGA high, the PEF A flag is forced high, regardless of the state of the A0–A35 inputs.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

I/O DESCRIPTION

PEFB

(port B)

Port-B parity error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35 with the most-significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state of ODD/EVEN

The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having CSB

low, ENB

high, W/R

B low, SIZ1 and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the

B0–B35 inputs.

PGA I

Port-A parity generation. Parity is generated for data reads from the mail2 register when PGA is high. The type of parity generated is selected by the state of ODD/EVEN

. Bytes are organized as A0–A8, A9–A17, A18–A26, and

A27–A35. The generated parity bits are output in the most-significant bit of each byte.

PGB I

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated is selected by the state of ODD/EVEN

. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.

The generated parity bits are output in the most-significant bit of each byte.

RST

Reset. T o reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST

is low. This sets the AF, MBF1, and MBF2 flags high and the EF, AE, and FF flags low. The low-to-high

transition of RST

latches the status of the FS1 and FS0 inputs to select AF flag and AE flag offset.

SIZ0 SIZ1

(port B)

Port-B bus size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.

SW0 SW1

(port B)

Port-B byte swap selects. At the beginning of each long-word FIFO read, one of four modes of byte-order swapping is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection.

W/RA

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R

A is high.

W/RB

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/R

B is high.

detailed description

reset

The SN74ABT3613 is reset by taking the reset (RST

) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces FF

low, EF low, AE low, and the

high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FF is set high after two

low-to-high transitions of CLKA. The device must be reset after power up before data is written to its memory . A low-to-high transition on the RST

input loads the AF and AE offset register (X) with the value selected by the

flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

T able 1. Flag Programming

FS1 FS0 RST

AF/AE FLAG

OFFSET REGISTER (X)

H H ↑ 16 H L ↑ 12

L H ↑ 8 L L ↑ 4

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FIFO write/read operation

The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA

) and the port-A

write/read select (W/R

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0–A35 outputs are active when both CSA

and W/RA are low. Data is loaded into the FIFO from the

A0–A35 inputs on a low-to-high transition of CLKA when CSA

is low, W/RA is high, ENA is high, MBA is low,

and FFA

is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

A0–A35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, mail2 register None L L H L ↑ Active, mail2 register None L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/R

B). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is

high. The B0–B35 outputs are active when both CSB

and W/RB are low. Data is read from the FIFO to the

B0–B35 outputs by a low-to-high transition of CLKB when CSB

is low, W/RB is low, ENB is high, EFB is high,

and either SIZ0 or SIZ1 is low (see Table 3).

Table 3. Port-B Enable Function Table

CSB W/RB ENB SIZ1, SIZ0 CLKB

B0–B35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None L H L X X In high-impedance state None L H H One, both low ↑ In high-impedance state None L H H Both high ↑ In high-impedance state Mail2 write L L L One, both low X Active, FIFO output register None L L H One, both low ↑ Active, FIFO output register FIFO read L L L Both high X Active, mail1 register None L L H Both high ↑ Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read selects (W/R

A, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setup- and hold-time window of the cycle.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. FF

and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows

the relationship of each port flag to the level of FIFO fill.

Table 4. FIFO Flag Operation

NUMBER OF 36-BIT

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

WORDS IN THE FIFO

†

EF AE AF FF

0 L L H H

1 to X H L H H

(X + 1) to [64 – (X + 1)] H H H H

(64 – X) to 63 H H L H

64 H H L L

†

X is the value in the AE flag and AF flag offset register.

empty flag (EF)

The FIFO EF is synchronized to the port clock that reads data from its array (CLKB). When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored. When reading the FIFO with a byte or word size on port B, EF

is set low when

the fourth byte or second word of the last long word is read. The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written

to the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles. An EF is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The FIFO EF

is set high by the second low-to-high transition of CLKB and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time t

sk1

, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization

cycle (see Figure 9).

full flag (FF)

The FIFO FF is synchronized to the port clock that writes data to its array (CLKA). When FF is high, a memory location is free in the SRAM to receive new data. No memory locations are free when FF

is low and attempted

writes to the FIFO are ignored. Each time a word is written to the FIFO, the write pointer is incremented. From the time a word is read from the

FIFO, the previous memory location is ready to be written in a minimum of three CLKA cycles. FF

is low if fewer than two CLKA cycles have elapsed since the next memory-write location has been read. The second low-to-high transition on the FF

synchronizing clock after the read sets the FF high and data can be written in

the following clock cycle. A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs

at time t

sk1

, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization

cycle (see Figure 10).

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

almost-empty flag (AE)

The FIFO AE flag is synchronized to the port clock that reads data from its array (CLKB). The almost-empty state is defined by the value of the AF

and AE offset register (X). This register is loaded with one of four preset values

during a device reset (see

reset

). An AE flag is low when the FIFO contains X or fewer long words in memory

and is high when the FIFO contains (X + 1) or more long words. Two low-to-high transitions of CLKB are required after a FIFO write for the AE

flag to reflect the new level of

fill; therefore, the AE

flag of a FIFO containing (X + 1) or more long words remains low if two CLKB cycles have

not elapsed since the write that filled the memory to the (X + 1) level. An AE

flag is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time t

sk2

, or greater, after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 11).

almost-full flag (AF)

The FIFO AF flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full state is defined by the value of the AF

and AE offset register (X). This register is loaded with one of four preset values

during a device reset (see

reset

). An AF flag is low when the FIFO contains (64 – X) or more long words in

memory and is high when the FIFO contains [64 – (X + 1)] or less long words. Two low-to-high transitions of CLKA are required after a FIFO read for the AF

flag to reflect the new level of fill;

therefore, the AF

flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two CLKA cycles have

not elapsed since the read that reduced the number of long words in memory to [64 – (X + 1)]. An AF

flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of long words in memory to [64 – (X + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time t

sk2

, or greater, after the read that reduces the number of long words in memory to [64 – (X + 1)].

Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 12).

mailbox registers

Two 36-bit bypass registers (mail1, mail2) are on board the SN74ABT3613 to pass command and control information between port A and port B without putting it in queue. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by CSA

, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB writes B0–B35 data to the mail2 register when a port-B write is selected by (CSB

, W/RB, and ENB) and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding

flag (MBF1

or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low.

When the port-B data outputs (B0–B35) are active, the data on the bus comes from the FIFO output register when either one or both SIZ1 and SIZ0 are low and from the mail1 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1

) is set high by a rising CLKB edge when a port-B read is selected by CSB, W/RB,

and ENB, and both SIZ1 and SIZ0 are high. The mail2 register flag (MBF2

) is set high by a rising CLKA edge

when a port-A read is selected by CSA

, W/RA, and ENA and MBA is high. The data in the mail register remains

intact after it is read and changes only when new data is written to the register.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

dynamic bus sizing

The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from the FIFO. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths.

The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE

) input are stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1.

Only 36-bit long-word data is written to or read from the FIFO memory on the SN74ABT3613. Bus-matching operations are done after data is read from the FIFO RAM. Port-B bus sizing does not apply to mail-register operations.

Read From FIFO

Write to FIFO

(a) LONG-WORD SIZE

1st: Read From FIFO

2nd: Read From FIFO

(b) WORD SIZE – BIG ENDIAN

BYTE ORDER ON PORT A:

A35 A27 A26 A18 A17 A9 A8 A0

B35 B27 B26 B18 B17 B9 B8 B0

XLL

SIZ1 SIZ0

ABCD

B35 B27 B26 B18 B17 B9 B8 B0

LLH

SIZ1 SIZ0

1st: Read From FIFO

2nd: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 B0

HLH

SIZ1 SIZ0

Figure 1. Dynamic Bus Sizing

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1st: Read From FIFO

2nd: Read From FIFO

3rd: Read From FIFO

4th: Read From FIFO

(d) BYTE SIZE – BIG ENDIAN

B35 B27 B26 B18 B17 B9 B8 B0

LHL

SIZ1 SIZ0

ÎÎÎ

2nd: Read From FIFO

ÎÎÎ

3rd: Read From FIFO

ÎÎÎ

4th: Read From FIFO

(e) BYTE SIZE – LITTLE ENDIAN

1st: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 B0

HHL

BE SIZ1 SIZ0

Figure 1. Dynamic Bus Sizing (Continued)

bus-matching FIFO reads

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire long word immediately shifts to the FIFO output register upon a read. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO output register with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO reads with the same bus-size implementation output the rest of the long word to the FIFO output register in the order shown by Figure 1.

Each FIFO read with a new bus-size implementation automatically unloads data from the FIFO RAM to its output register and auxiliary registers. Implementing a new port-B bus size and performing a FIFO read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread data in these registers.

When reading data from FIFO in byte or word format, the unused B0–B35 outputs remain inactive but static, with the unused FIFO output register bits holding the last data value to decrease power consumption.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

port-B mail-register access

In addition to selecting port-B bus sizes for FIFO reads, the port-B bus-size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed immediately. Any bus-sizing operation that is underway is unaffected by the mail-register access. After the mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 2 shows the previous bus-size selection is preserved when the mail registers are accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE

_Q.

MUX

CLKB

SIZ0 SIZ1

SIZ0_Q SIZ1_Q BE

Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register

byte swapping

The byte-order arrangement of data read from the FIFO can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is rearranged within the long word, but the bit order within the bytes remains constant.

Byte arrangement is chosen by the port-B swap-select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from the FIFO. The byte order chosen on the first byte or first word of a new long-word read from the FIFO is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent reads. Figure 3 is an example of the byte-order swapping available for long-word reads. Performing a byte swap and bus size simultaneously for a FIFO read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(a) NO SWAP

(b) BYTE SWAP

(d) BYTE-WORD SWAP

SW1 SW0

A35 A27 A26 A18 A17 A9 A8 A0

AB CD

DC BA

CD AB

BA DC

B35 B27 B26 B18 B17 B9 B8 B0

A35 A27 A26 A18 A17 A9 A8 A0

B35 B27 B26 B18 B17 B9 B8 B0

A35 A27 A26 A18 A17 A9 A8 A0

B35 B27 B26 B18 B17 B9 B8 B0

A35 A27 A26 A18 A17 A9 A8 A0

B35 B27 B26 B18 B17 B9 B8 B0

Figure 3. Byte Swapping for FIFO Reads (Long-Word Size Example)

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

parity checking

The port-A data inputs (A0–A35) and port-B data inputs (B0–B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low level on the port-A parity error flag (PEFA

). A parity failure on one or more bytes of the port-B data inputs that

are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB

). Odd

or even parity checking can be selected and the parity-error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN

) select input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding port parity-error flag (PEFA

, PEFB) output. Port-A bytes are arranged as A0–A8, A9–A17, A18–A26, and A27–A35. Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, and its valid bytes are those used in a port-B bus-size implementation. When odd/even parity is selected, a port parity-error flag (PEFA

, PEFB) is

low if any valid byte on the port has an odd/even number of low levels applied to the bits. The four parity trees used to check the A0–A35 inputs are shared by the mail2 register when parity generation

is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is selected with CSA

low, ENA high, W/RA low, MBA high, and PGA high, PEFA is held high, regardless of the levels applied to the A0–A35 inputs. Likewise, the parity trees used to check the B0–B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB

low, ENB high, W/RB low , both SIZ0 and SIZ1 high,

and PGB high, PEFB

is held high, regardless of the levels applied to the B0–B35 inputs.

parity generation

A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the SN74ABT3613 to generate parity bits for port reads from a FIFO or mailbox register . Port-A bytes are arranged as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35 with the most-significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte, regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN

select. The generated parity bits are substituted for the levels originally written to the

most-significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the

output register. The port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN

) have setupand hold-time constraints to the port-A clock (CLKA) and the port-B parity-generate select (PGB) and ODD/EVEN

select have setup- and hold-time constraints to the port-B clock (CLKB). These timing constraints

apply only for a rising clock edge used to read a new long word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0–B35) to check parity . The

circuit used to generate parity for the mail2 data is shared by the port-A bus (A0–A35) to check parity . The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port-chip select (CSA

CSB

) is low, enable (ENA, ENB) is high, and write/read select (W/RA, W/RB) input is low, the mail register is selected (MBA is high for port A; both SIZ0 and SIZ1 are high for port B), and port parity-generate select (PGA, PGB) is high. Generating parity for mail-register data does not change the contents of the register.

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pd(C-EF)

CLKA

CLKB

RST

0,1

h(FS)

su(FS)

h(RS)

su(RS)

FS1, FS0

pd(C-FF)

pd(C-AE)

MBF1,

MBF2

pd(R-F)

pd(C-AF)

Figure 4. Device Reset Loading the X Register With the Value of Eight

ММММММММ

su(D)

МММММММ

CLKA

FFA

CSA

†

su(EN)

w(CLKL)

w(CLKH)

h(EN)

su(EN)

ППППППП

ООООООО

W/RA

MBA

ENA

A0–A35

†

ООООООО

su(EN)

h(EN)

su(EN)

h(EN)

su(EN)

h(EN)

h(D)

h(EN)

No Operation

ÌÌ

ODD/

EVEN

Valid

PEFA

Valid

pd(D-PE)

High

†

Written to the FIFO

Figure 5. FIFO Write Cycle

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(PG)

SIZ1,

SIZ0

W/RB

CLKB

CSB

ENB

B0–B35

su(EN) t

h(EN)

PGB, ODD/

EVEN

High

SW1,

SW0

su(SW) t

h(SW)

(0, 0) Not (1, 1)

†

(0, 0)

su(SZ)

h(SZ)

su(SZ)

su(EN)

h(EN)

Not (1, 1)

†

h(PG)

Previous Data W1

‡

dis

No Operation

†

SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.

‡

Data read from the FIFO

DATA SWAP FOR FIFO LONG-WORD READS

FIFO-DATA WRITE

SWAP MODE FIFO-DATA READ

A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0 B35–B27 B26–B18 B17–B9 B8–B0

A B C D L L A B C D A B C D L H D C B A A B C D H L C D A B A B C D H H B A D C

Figure 6. FIFO Long-Word Read Cycle

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SIZ1,

SIZ0

W/RB

CLKB

CSB

ENB

B0–B17

su(EN)

h(EN)

PGB,

ODD/

EVEN

High

SW1,

SW0

su(SW)

h(SW)

(0, 1) Not (1, 1)

†

(0, 1)

su(SZ)

h(SZ)

su(SZ)

Not (1, 1)

†

su(PG)

h(PG)

Previous Data Read 1 Read 2

dis

No Operation

Little

Endian

‡

Big

Endian

‡

B18–B35

Previous Data Read 1 Read 2

dis

†

SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.

‡

Unused word B0–B17 or B18–B35 holds last FIFO output-register data for word-size reads.

DATA SWAP FOR FIFO-WORD READS

FIFO-DATA READ

FIFO-DATA WRITE

SWAP MODE

READ

BIG ENDIAN LITTLE ENDIAN

A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0

B35–B27 B26–B18 B17–B9 B8–B0

1 A B C D

ABCDL

2 C D A B 1 D C B A

ABCDL

2 B A D C 1 C D A B

ABCDH

2 A B C D 1 B A D C

ABCDH

2 D C B A

Figure 7. FIFO-Word Read Cycle

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(1, 0)

SIZ1, SIZ0

W/R

CLKB

CSB

ENB

SW1, SW0

Not (1, 1)

†

High

su(EN)

h(EN)

No Operation

su(SW)

h(SW)

su(SZ)

(1, 0)

Not (1, 1)

†

(1, 0) (1, 0)

Not (1, 1)

†

Not (1, 1)

†

PGB,

ODD/EVEN

su(PG)

h(PG)

B0–B8

Read 1 Read 2

Read 3 Read 4

dis

B27–B35

Read 1 Read 2

Previous Data

Read 3 Read 4

dis

h(SZ)

Previous Data

†

SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.

NOTE A: Unused bytes hold the last FIFO output-register data for byte-size reads.

Figure 8. FIFO-Byte Read Cycle

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DATA SWAP FOR FIFO-BYTE READS

FIFO-DATA READ

FIFO-DATA WRITE SWAP MODE

READ

NO.

BIG

ENDIAN

LITTLE

ENDIAN

A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0 B35–B27 B8–B0

1 A D 2 B C

ABCDL

3 C B 4 D A 1 D A 2 C B

ABCDL

3 B C 4 A D 1 C B 2 D A

ABCDH

3 A D 4 B C 1 B C 2 A D

ABCDH

3 D A 4 C B

Figure 8. FIFO-Byte Read Cycle (Continued)

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

h(EN)

su(EN)

CLKA

A0–A35

MBA

ENA

CSA

W/RA

CLKB

CSB

W/RB

SIZ1, SIZ0

ENB

B0–B35

su(EN)

w(CLKH)

w(CLKL)

pd(C-EF)

FIFO Empty

Low

High

w(CLKL)

w(CLKH)

High

h(EN)

su(EN)

h(D)

su(D)

sk1

†

Low

pd(C-EF)

h(EN)

†

sk1

is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition high in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than t

sk1

, the transition of EF

high may occur one CLKB cycle later than shown.

NOTE A: Port-B size of long word is selected for the FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EF

is set low by the last

word or byte read from the FIFO, respectively.

Figure 9. EF-Flag Timing and First Data Read When the FIFO Is Empty

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKB

B0–B35

SIZ1, SIZ0

ENB

CSB

W/RB

CLKA

CSA

W/RA

MBA

ENA

A0–A35

su(EN)

h(EN)

su(EN)

pd(C-FF)

FIFO Full

sk1

†

Previous Word in the FIFO Output Register Next Word From the FIFO

w(CLKH)

w(CLKL)

To FIFO

Low

High

h(EN)

su(EN)

h(D)

su(D)

High

w(CLKH)

w(CLKL)

pd(C-FF)

†

sk1

is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition high in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than t

sk1

, FF

may transition high one CLKA cycle later than shown.

NOTE A: Port-B size of long word is selected for the FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t

sk1

is referenced from the

rising CLKB edge that reads the first word or byte of the long word, respectively.

Figure 10. FF-Flag Timing and First Available Write When the FIFO Is Full

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

su(EN)

CLKA

ENB

ENA

h(EN)

su(EN)

sk2

†

pd(C-AE)

X Long Words in the FIFO

CLKB

pd(C-AE)

h(EN)

(X + 1) Long Words in the FIFO

†

sk2

is the minimum time between a rising CLKA edge and a rising CLKB edge for AE

to transition high in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than t

sk2

, AE

may transition high one CLKB cycle later than shown.

NOTES: A. FIFO write (CSA

= L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L)

B. Port-B size of long word is selected for FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t

sk2

is referenced to the

first word or byte read of the long word, respectively.

Figure 11. AE When the FIFO Is Almost Empty

pd(C-AF)

su(EN)

CLKA

ENB

ENA

su(EN)

h(EN)

[64 – (X + 1)] Long Words in the FIFO

h(EN)

sk2

‡

CLKB

(64 – X) Long Words in the FIFO

‡

sk2

is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than t

sk2

, AF

may transition high one CLKB cycle later than shown.

NOTES: A. FIFO write (CSA

= L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L)

B. Port-B size of long word is selected for FIFO read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t

sk2

is referenced from the

first word or byte read of the long word, respectively.

Figure 12. AF When the FIFO Is Almost Full

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

CSA

W/RA

su(EN)

h(D)

MBA

ENA

A0–A35

ÌÌÌ

h(EN)

su(D)

CLKB

h(EN)

CSB

su(EN)

pd(C-MF)

MBF1

W/RB

SIZ1, SIZ0

ENB

B0–B35

FIFO Output Register

W1 (remains valid in mail1 register after read)

pd(C-MR)

dis

pd(M-DV)

NOTE A: Port-B parity generation off (PGB = L)

Figure 13. Mail1 Register and MBF1 Flag

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKB

CSB

W/RA

SIZ1, SIZ0

ENB

A0–A35

CLKA

CSA

MBF2

W/RB

MBA

ENA

B0–B35

su(EN)

h(D)

h(EN)

su(D)

h(EN)

su(EN)

pd(C-MF)

W1 (remains valid in mail2 register after read)

pd(C-MR)

dis

h(SZ)

su(SZ)

NOTE A: Port-A parity generation off (PGA = L)

Figure 14. Mail2 Register and MBF2 Flag

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MBA

pd(E-PE)

Valid

pd(O-PE)

ODD/EVEN

W/RA

PGA

PEFA

Valid

pd(O-PE)

Valid Valid

NOTE A: CSA

= L and ENA = H

Figure 15. ODD/EVEN, W/RA, MBA, and PGA to PEFA

pd(E-PE)

Valid

pd(O-PE)

DD/EVEN

W/R

PGB

PEFB

SIZ1,

SIZ0

Valid

pd(O-PE)

Valid Valid

NOTE A: CSB

= L and ENB = H

Figure 16. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ODD/EVEN

CSA

PGA

A8, A17,

A26, A35

MBA

Generated Parity

Low

W/R

pd(E-PB)

pd(O-PB)

Generated Parity

pd(E-PB)

Mail2 Data

NOTE A: ENA = H

Figure 17. Parity Generation When Reading From the Mail2 Register

DD/EVEN

CSB

PGB

B8, B17,

B26, B35

SIZ1,

SIZ0

Generated Parity

Low

W/R

Mail1

Data

pd(E-PB)

pd(O-PB)

Generated Parity

pd(E-PB)

Mail1 Data

pd(M-DV)

NOTE A: ENB = H

Figure 18. Parity Generation When Reading From the Mail1 Register

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): PCB package 28°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PQ package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

MIN MAX UNIT

Supply voltage 4.5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current –4 mA

Low-level output current 8 mA

Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

VCC = 4.5 V, IOH = –4 mA 2.4 V

VCC = 4.5 V, IOL = 8 mA 0.5 V

VCC = 5.5 V, VI = VCC or 0 ±50 µA

VCC = 5.5 V, VO = VCC or 0 ±50 µA

Outputs high 60

VCC = 5.5 V, IO = 0 mA, VI = VCC or GND

Outputs low

130

Outputs disabled 60

VI = 0, f = 1 MHz 4 pF

VO = 0, f = 1 MHz 8 pF

‡

All typical values are at VCC = 5 V, TA = 25°C.

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 4 through 19)

’ABT3613-15 ’ABT3613-20 ’ABT3613-30

MIN MAX MIN MAX MIN MAX

UNIT

clock

Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz

Clock cycle time, CLKA or CLKB 15 20 30 ns

w(CLKH)

Pulse duration, CLKA and CLKB high 6 8 12 ns

w(CLKL)

Pulse duration, CLKA and CLKB low 6 8 12 ns

su(D)

Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑ 4 5 6 ns

su(EN)

Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB

, W/RB, and ENB before CLKB↑

5 5 6 ns

su(SZ)

Setup time, SIZ0, SIZ1, and BE before CLKB↑ 4 5 6 ns

su(SW)

Setup time, SW0 and SW1 before CLKB↑ 5 7 8 ns

su(PG)

Setup time, ODD/EVEN and PGB before CLKB↑

†

4 5 6 ns

su(RS)

Setup time, RST low before CLKA↑ or CLKB↑

‡

5 6 7 ns

su(FS)

Setup time, FS0 and FS1 before RST high 5 6 7 ns

h(D)

Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑ 1 1 1 ns

h(EN)

Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB

, W/RB, and ENB after CLKB↑

1 1 1 ns

h(SZ)

Hold time, SIZ0, SIZ1, and BE after CLKB↑ 2 2 2 ns

h(SW)

Hold time, SW0 and SW1 after CLKB↑ 0 0 0 ns

h(PG)

Hold time, ODD/EVEN and PGB after CLKB↑

†

0 0 0 ns

h(RS)

Hold time, RST low after CLKA↑ or CLKB↑

‡

5 6 7 ns

h(FS)

Hold time, FS0 and FS1 after RST high 4 4 4 ns

sk1

Skew time between CLKA↑ and CLKB↑ for EF and FF 8 8 10 ns

sk2

Skew time between CLKA↑ and CLKB↑ for AE and AF 9 16 20 ns

†

Applies only for a clock edge that does a FIFO read

‡

Requirement to count the clock edge as one of at least four needed to reset a FIFO

Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle.

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

= 30 pF (see Figures 4 through 19)

’ABT3613-15 ’ABT3613-20 ’ABT3613-30

PARAMETER

MIN MAX MIN MAX MIN MAX

UNIT

max

66.7 50 33.4 MHz

Access time, CLKA↑ to A0–A35 and CLKB↑ to B0–B35 2 10 2 12 2 15 ns

pd(C-FF)

Propagation delay time, CLKA↑ to FF 2 10 2 12 2 15 ns

pd(C-EF)

Propagation delay time, CLKB↑ to EF 2 10 2 12 2 15 ns

pd(C-AE)

Propagation delay time, CLKB↑ to AE 2 10 2 12 2 15 ns

pd(C-AF)

Propagation delay time, CLKA↑ to AF 2 10 2 12 2 15 ns

pd(C-MF)

Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and CLKB↑ to MBF2

low or MBF1 high

1 9 1 12 1 15 ns

pd(C-MR)

Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to A0–A35

‡

3 11 3 12 3 15 ns

pd(C-PE)

Propagation delay time, CLKB↑ to PEFB 2 11 2 12 2 13 ns

pd(M-DV)

Propagation delay time, SIZ1, SIZ0 to B0–B35 valid 1 11 1 11.5 1 12 ns

pd(D-PE)

Propagation delay time, A0-A35 valid to PEFA

valid; B0–B35 valid to PEFB valid

3 10 3 11 3 13 ns

pd(O-PE)

Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns

pd(O-PB)

Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35)

2 12 2 13 2 15 ns

pd(E-PE)

Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA

; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB

1 11 1 12 1 14 ns

pd(E-PB)

Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB

, ENB, W/RB,

SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)

3 12 3 13 3 14 ns

pd(R-F)

Propagation delay time, RST

to AE, EF low and AF, MBF1, MBF2 high

1 15 1 20 1 25 ns

Enable time, CSA and W/RA low to A0–A35 active and CSB

low and W/RB high to B0–B35 active

2 10 2 12 2 14 ns

dis

Disable time, CSA or W/RA high to A0–A35 at high impedance and CSB

high or W/RB low to B0–B35 at high impedance

1 8 1 9 1 11 ns

†

Writing data to the mail1 register when the B0–B35 outputs are active and SIZ1 and SIZ0 are high

‡

Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high

Applies only when a new port-B bus size is implemented by the rising CLKB edge

Applies only when reading data from a mail register

SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

1.5 V1.5 V

3 V

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data,

Enable

Input

1.5 V 1.5 V

3 V

GND

High-Level

Input

Low-Level

Input

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

1.5 V 1.5 V

1.5 V1.5 V

3 V

GND

In-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ

≈ 3 V

PHZ

1.5 V 1.5 V

3 V

GND

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PZL

1.5 V

≈ 0 V

1.5 V

PZH

Output Enable

Low-Level

Output

High-Level

Output

From Output

Under Test

30 pF (see Note A)

680 Ω

1.1 kΩ

5 V

LOAD CIRCUIT

NOTES: A. Includes probe and jig capacitance

B. t

PZL

and t

PZH

are the same as t

C. t

PLZ

and t

PHZ

are the same as t

dis

Figure 19. Load Circuit and Voltage Waveforms

SN74ABT3613

64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

– Supply Current – mA

CC(f)

SUPPLY CURRENT

CLOCK FREQUENCY

clock

– Clock Frequency – MHz

150

100

01020304050

200

250

300

60 70 80

350

400

data

= 1/2 f

clock

TA = 25°C CL = 0 pF

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

Figure 20

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SN74ABT3613-20PCB, SN74ABT3613-20PQ, SN74ABT3613-30PCB, SN74ABT3613-30PQ, SN74ABT3613-15PCB Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual