Texas Instruments SN74ABT16863DL, SN74ABT16863DLR Datasheet

SN54ABT16863, SN74ABT16863

18-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS225C – JUNE 1992 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings

description

The ’ABT16863 are 18-bit noninverting
transceivers designed for asynchronous
communication between data buses. The
control-function implementation minimizes
external timing requirements.

The ’ABT16863 can be used as two 9-bit
transceivers or one 18-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB

or OEBA)

inputs.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16863 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16863 is characterized for operation from –40°C to 85°C.

SN54ABT16863 ...WD PACKAGE

SN74ABT16863 . . . DL PACKAGE

(TOP VIEW)

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19
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23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
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41
40
39
38
37
36
35
34
33
32
31
30
29

1OEAB

1B1
1B2

GND

1B3
1B4

V

CC

1B5
1B6
1B7

GND

1B8

1B9
GND
GND

2B1

2B2
GND

2B3

2B4

2B5

V

CC

2B6

2B7
GND

2B8

2B9

2OEAB

1OEBA
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V

CC

2A6
2A7
GND
2A8
2A9
2OEBA

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABT16863, SN74ABT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS225C – JUNE 1992 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each 9-bit section)

INPUTS

OEAB OEBA

OPERATION

H L B data to A bus
L H A data to B bus
H H Isolation

logic symbol

†

1A2

54

1A3

52

1A4

51

1A5

49

1B2

3

1B3

5

1B4

6

1B5

8

1OEBA
1OEAB
2OEBA
2OEAB

EN1

56

1A1

55

1B1

2

EN2

1

EN3

29

EN4

28

1A6

48

1A7

47

1A8

45

1A9

44

1B6

9

1B7

10

1B8

12

1B9

13

2A1

41

2A2

40

2A3

38

2A4

37

2A5

36

2B1

16

2B2

17

2B3

19

2B4

20

2B5

21

2A6

34

2A7

33

2A8

31

2A9

30

2B6

23

2B7

24

2B8

26

2B9

27

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1
1

1
1

1

3

2

4

SN54ABT16863, SN74ABT16863

18-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS225C – JUNE 1992 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1OEBA

1OEAB

1A1 1B1

To Eight Other Channels

56

1

55 2

2OEBA

2OEAB

2A1 2B1

To Eight Other Channels

29

28

41 16

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, V

O

–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT16863 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT16863 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT16863 SN74ABT16863

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

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design phase of development. Characteristic data and other
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change or discontinue these products without notice.