SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Parity-Error Flag With Parity
Generator/Checker
D
Latch for Storage of the Parity-Error Flag
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16853 dual 8-bit to 9-bit parity
transceivers are designed for communication
between data buses. When data is transmitted
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the
B bus to the A bus, with its corresponding parity
bit, the open-collector parity-error (ERR
indicates whether or not an error in the B data has
occurred. The output-enable (OEA
inputs can be used to disable the device so that
the buses are effectively isolated. The ’ABT16853
provide true data at the outputs.
) output
and OEB)
SN54ABT16853 ...WD PACKAGE
SN74ABT16853 . . . DGG OR DL PACKAGE
1OEB
1ERR
2ERR
2OEB
1LE
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2LE
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16853, SN74ABT16853
LHX
X
NANAAHNA
HLXLNA
BNANA
§
H
H
XZZ
Z
LLX
X
NANAALNA
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
description (continued)
The SN54ABT16853 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16853 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEB OEA CLR
H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error-flag register
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume ERR
§
In this mode, ERR
LE
H H X NC
LH X
X L L Odd
X L H Even L
(when clocked) shows inverted parity of the A bus.
AI
Σ OF H
Odd
Even
Odd
Even
was previously high.
†
BI
Σ OF H
Odd
Even
OUTPUT AND I/O
A B PARITY
L
H
ERR
H
L
H
H
‡
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Isolation
(parity check)
A data to B bus and
generate inverted parity
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ERR
L
LHXHPass
HHX
Store
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
logic diagram (each transceiver) (positive logic)
SN54ABT16853, SN74ABT16853
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
A1–A8
OEB
OEA
LE
8
8x
EN
8
8
MUX
1
1
1
1
G1
8x
EN
8
9
2k
P
8
B1–B8
PARITY
ERR
CLR
ERROR-FLAG FUNCTION TABLE
INPUTS
CLR LE
H L
L H X X H Clear
†
State of ERR before changes at CLR, LE, or point P
INTERNAL
TO DEVICE
POINT P
L
L X L
X
H HH
OUTPUT
ERR
LL
L L
H H
n–1
OUTPUT
†
L
FUNCTION
Sample
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
error-flag waveforms
OEB
H
L
OEA
Bi + PARITY
LE
CLR
ERR
Pass Store Sample
Clear
H
L
Even
Odd
H
L
H
L
H
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
: SN54ABT16853 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ABT16853 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
VOLV
V
V
I
V
V
V
GND
A
V
CC
SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT16853 SN74ABT16853
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
OH
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
IK
OH
V
hys
I
OH
I
off
I
CEX
I
I
IL
I
O
I
OZH
I
OZL
I
CC
∆I
CC
C
i
C
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§
The parameters I
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output voltage ERR 5.5 5.5 V
High-level output current Except ERR –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
TA = 25°C SN54ABT16853 SN74ABT16853
MIN TYP†MAX MIN MAX MIN MAX
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 3 2.5
All outputs
except ERR
ERR VCC = 4.5 V, VOH = 5.5 V 20 20 20 µA
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
Control inputs
A or B ports
A or B ports VCC = 0, VI = GND –50 –50 –50 µA
‡
§
§
A or B ports
¶
Control inputs VI = 2.5 V or 0.5 V 3 pF
A or B ports VO = 2.5 V or 0.5 V 9 pF
VCC = 5 V, IOH = –3 mA 3 3.4 3 3
= 4.5
CC
= 4.5
CC
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC =5.5 V, VO = 2.7 V 50 50 50 µA
VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
OZH
and I
include the input leakage current.
OZL
IOH = –24 mA 2
IOH = –32 mA 2* 2.7 2
IOL = 24 mA 0.25 0.55 0.55
IOL = 64 mA 0.3 0.55* 0.55
100 mV
=
or
I
CC
Outputs high 1.5 2 2 2
Outputs low 32 40 40 40
Outputs disabled 1 2 2 2
±1 ±1 ±1
±100 ±100 ±100
50 50 50 µA
CC
0 V
CC
V
µ
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT16853, SN74ABT16853
twPulse duration
ns
tsuSetup time
ns
thHold time
ns
(INPUT)
(OUTPUT)
A or B
B or A
ns
A
OE
PARITY
ns
OE
A or B
ns
OE
A or B
ns
OE
PARITY
ns
OE
PARITY
ns
LE
ERR
ns
A, B, or PARITY
ERR
ns
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
LE high or low 8.5 8.5 8.5
CLR low 4 4 4
p
A, B, and PARITY before LE↓ 10 10 10
CLR before LE↓ 0 0 0
A, B, and PARITY after LE↓ 0 0 0
CLR after LE↓ 0 0 0
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1.5 2.5 3.3 1.5 4.2 1.5 4.1
2 3.1 3.9 2 4.5 2 4.3
2 4.6 5.9 2 7.3 2 7.1
2 4.8 6.2 2 7.6 2 7.2
2 3.7 5.1 2 5.9 2 5.7 ns
2 3.9 4.9 2 5.8 2 5.6
2.5 4.3 5.1 2.5 6.2 2.5 6
2 3.6 4.5 2 5.5 2 5.4
1.5 3 3.8 1.5 4.7 1.5 4.3
2 3.6 5 2 5.8 2 5.7
2.5 4.4 5.8 2.5 6.7 2.5 6.5
1.5 3.2 4 1.5 4.8 1.5 4.7
1.5 2.9 3.7 1.5 4.2 1.5 4.1
2 3.5 4.2 2 5 2 4.8
2 3.4 4.4 2 5.2 2 4.9
2 4.5 6.3 2 7.5 2 7.2
2 4.8 6.3 2 7.7 2 7.4
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
FROM
or
CLR ERR
TO
SN54ABT16853 SN74ABT16853
SN54ABT16853 SN74ABT16853
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
500 Ω
500 Ω
LOAD CIRCUIT
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.5 V1.5 V
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
GND
OH
OL
OH
OL
Open
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
ERR S1
t
(see Note E)
PHL
t
(see Note F)
PLH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
Open
7 V
Open
1.5 V
t
7 V
7 V
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns
D. The outputs are measured one at a time with one transition per measurement.
E. t
is measured at 1.5 V.
PHL
F. t
is measured at VOL + 0.3 V.
PLH
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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