Texas Instruments SN74ABT16853DGGR, SN74ABT16853DL, SN74ABT16853DLR Datasheet
SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Parity-Error Flag With Parity
Generator/Checker
D
Latch for Storage of the Parity-Error Flag
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16853 dual 8-bit to 9-bit parity
transceivers are designed for communication
between data buses. When data is transmitted
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the
B bus to the A bus, with its corresponding parity
bit, the open-collector parity-error (ERR
indicates whether or not an error in the B data has
occurred. The output-enable (OEA
inputs can be used to disable the device so that
the buses are effectively isolated. The ’ABT16853
provide true data at the outputs.
) output
and OEB)
SN54ABT16853 ...WD PACKAGE
SN74ABT16853 . . . DGG OR DL PACKAGE
1OEB
1ERR
2ERR
2OEB
1LE
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2LE
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16853, SN74ABT16853
LHX
X
NANAAHNA
HLXLNA
BNANA
§
H
H
XZZ
Z
LLX
X
NANAALNA
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
description (continued)
The SN54ABT16853 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16853 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEB OEA CLR
H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error-flag register
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume ERR
§
In this mode, ERR
LE
H H X NC
LH X
X L L Odd
X L H Even L
(when clocked) shows inverted parity of the A bus.
AI
Σ OF H
Odd
Even
Odd
Even
was previously high.
†
BI
Σ OF H
Odd
Even
OUTPUT AND I/O
A B PARITY
L
H
ERR
H
L
H
H
‡
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Isolation
(parity check)
A data to B bus and
generate inverted parity
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ERR
L
LHXHPass
HHX
Store
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
logic diagram (each transceiver) (positive logic)
SN54ABT16853, SN74ABT16853
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
A1–A8
OEB
OEA
LE
8
8x
EN
8
8
MUX
1
1
1
1
G1
8x
EN
8
9
2k
P
8
B1–B8
PARITY
ERR
CLR
ERROR-FLAG FUNCTION TABLE
INPUTS
CLR LE
H L
L H X X H Clear
†
State of ERR before changes at CLR, LE, or point P
INTERNAL
TO DEVICE
POINT P
L
L X L
X
H HH
OUTPUT
ERR
LL
L L
H H
n–1
OUTPUT
†
L
FUNCTION
Sample
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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