Texas Instruments SN74ABT16843DLR, SN74ABT16843DGGR, SN74ABT16843DL Datasheet

SN54ABT16843, SN74ABT16843

18-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS223E – OCTOBER 1992 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Impedance State During Power Up
and Power Down

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’ABT16843 18-bit bus-interface D-type
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.

The ’ABT16843 can be used as two 9-bit latches
or one 18-bit latch. The 18 latches are transparent
D-type latches. The device provides true data at
its outputs.

A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are in the
high-impedance state during power up and power
down. The outputs remain in the high-impedance
state while the device is powered down. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1CLR

1OE

1Q1

GND

1Q2
1Q3

V

CC

1Q4
1Q5
1Q6

GND

1Q7
1Q8
1Q9
2Q1
2Q2
2Q3

GND

2Q4
2Q5
2Q6

V

CC

2Q7
2Q8

GND

2Q9

2OE

2CLR

1LE
1PRE
1D1
GND
1D2
1D3
V

CC

1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V

CC

2D7
2D8
GND
2D9
2PRE
2LE

SN54ABT16843 ...WD PACKAGE

SN74ABT16843 . . . DGG OR DL PACKAGE

(TOP VIEW)

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critic al applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS223E – OCTOBER 1992 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16843 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16843 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 9-bit latch)

INPUTS

OUTPUT

PRE CLR OE

LE D

Q

L X L X X H
H LLXX L
H HLHL L
H HLHH H
H HLLX Q

0

X X H X X Z

SN54ABT16843, SN74ABT16843

18-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS223E – OCTOBER 1992 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1D1

1OE

1PRE

1Q1

1CLR

1LE

To Eight Other Channels

2D1

2OE

2PRE

2Q1

2CLR

2LE

To Eight Other Channels

2

55

1

54

27

30

28

29

42

3

15

56

S2
C1
1D
R

S2
C1
1D
R