Texas Instruments SN74ABT16833DGGR, SN74ABT16833DL, SN74ABT16833DLR Datasheet
SN54ABT16833, SN74ABT16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Typical V
(Output Ground Bounce)
OLP
< 1 V at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Parity-Error Flag With Parity
Generator/Checker
D
Register for Storage of Parity-Error Flag
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16833 consist of two noninverting 8-bit
to 9-bit parity bus transceivers and are designed
for communication between data buses. For each
transceiver, when data is transmitted from the
A bus to the B bus, an odd-parity bit is generated
and output on the parity I/O pin (1PARITY or
2PARITY). When data is transmitted from the
B bus to the A bus, 1PARITY (or 2PARITY) is
configured as an input and combined with the
B-input data to generate an active-low error flag if
odd parity is not detected.
SN54ABT16833 . . . WD PACKAGE
SN74ABT16833 . . . DGG OR DL PACKAGE
1OEB
1ERR
2ERR
2OEB
1CLK
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CLK
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
The error (1ERR
or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is
clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR)
is cleared (set high) by taking the clear (1CLR or 2CLR) input low.
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic
capability.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16833, SN74ABT16833
LHX
X
NANAAHNA
HLH↑NA
BNANA
H
H
XZZ
Z
Isolati
§
LLX
X
NANAALNA
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997
description (continued)
The SN54ABT16833 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16833 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEB OEA CLR
X X L X X X X NA NA H Check error-flag register
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume ERR
§
In this mode, ERR
CLK
H No↑ X NC
LNo↑ X
H ↑ Odd
H ↑ Even L
(when clocked) shows inverted parity of the A bus.
Ai
Σ OF H
Odd
Even
Odd
Even
was previously high.
†
Bi
Σ OF H
Odd
Even
OUTPUT AND I/O
A B PARITY
L
H
ERR
H
L
H
H
‡
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
on
A data to B bus and
generate inverted parity
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16833, SN74ABT16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol
†
Φ
PARITY XCVR
SN74ABT16833
1CLK
1CLR
1OEA
1OEB
2CLK
2CLR
2OEA
2OEB
1
A Bus B Bus
8
1ERR
1PARITY
2ERR
2PARITY
3
1ERR
54
1PARITY
26
2ERR
31
2PARITY
52
1
8
51
49
48
47
45
44
43
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1CLK
1CLR
1OEA
1OEB
2CLK
2CLR
2OEA
2OEB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2
55
56
1
27
30
29
28
5
6
8
9
10
12
13
14
15
2A1
16
2A2
17
2A3
19
2A4
20
2A5
21
2A6
23
2A7
24
2A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
A Bus B Bus
8
42
1
8
41
40
38
37
36
34
33
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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