Texas Instruments SN74ABT16825DL, SN74ABT16825DLR Datasheet

SN54ABT16825, SN74ABT16825

18-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS218C – JUNE 1992 – REVISED MA Y 1997

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’ABT16825 are 18-bit buffers and line drivers
designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices can be
used as two 9-bit buffers or one 18-bit buffer . They
provide true data.

The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1

or OE2) input is high, all nine affected

outputs are in the high-impedance state.

SN54ABT16825 . . . WD PACKAGE

SN74ABT16825 . . . DGG OR DL PACKAGE

1OE1

2OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6
1Y7

GND

1Y8

1Y9
GND
GND

2Y1

2Y2
GND

2Y3

2Y4

2Y5

V

CC

2Y6

2Y7
GND

2Y8

2Y9

(TOP VIEW)

56

1

55

2

54

3

53

4

52

5

51

6

50

7

49

8

48

9

47

10

46

11

45

12

44

13

43

14

42

15

41

16

40

17

39

18

38

19

37

20

36

21

35

22

34

23

33

24

32

25

31

26

30

27

29

28

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V

CC

2A6
2A7
GND
2A8
2A9
2OE2

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16825 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16825 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT16825, SN74ABT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS218C – JUNE 1992 – REVISED MA Y 1997

FUNCTION TABLE

(each 9-bit section)

INPUTS

OE2 A

OE1

L L L L

L LH H
H XX Z
X H X Z

OUTPUT

Y

logic symbol

†

1OE1
1OE2

2OE1
2OE2

1
56

28
29

55

1A1 1Y1

54

1A2

52

1A3 1Y3

51

1A4 1Y4

49

1A5 1Y5

48

1A6 1Y6

47

1A7 1Y7

45

1A8

44

1A9 1Y9

41

2A1 2Y1

40

2A2 2Y2

38

2A2 2Y3

37

2A3 2Y4

36

2A4 2Y5

34

2A5 2Y6

33

2A6

31

2A7 2Y8

30

2A8 2Y9

&

EN1

&

EN2

10
12
13
16
17
19
20
21
23
24
26
27

2
3

1Y2

5
6
8
9

1Y8

2Y7

1

2

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1A1

1
56

55

To Eight Other Channels

2OE1
2OE2

2

1Y1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2A1

1OE1
1OE2

2

28
29

41

To Eight Other Channels

16

2Y1