SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
(or 2T/R) is low, data flows
or
SN54ABT16657 . . . WD PACKAGE
SN74ABT16657 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
1T/R
55
1ODD/EVEN
54
1PARITY
53
GND
52
1B1
51
1B2
50
V
CC
49
1B3
48
1B4
47
1B5
46
GND
45
1B6
44
1B7
43
1B8
42
2B1
41
2B2
40
2B3
39
GND
38
2B4
37
2B5
36
2B6
35
V
CC
34
2B7
33
2B8
32
GND
31
2PARITY
30
2ODD/EVEN
29
2T/R
1OE
NC
1ERR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2ERR
NC
2OE
NC – No internal connection
Odd or even parity is selected by a logic high or low level, respectively , on the 1ODD/EVEN (or 2ODD/EVEN)
input. 1P ARITY (or 2P ARITY) carries the parity bit value; it is an output from the parity generator/checker in the
transmit mode and an input to the parity generator/checker in the receive mode.
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2P ARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN
) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1P ARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16657, SN74ABT16657
NUMBER OF A OR B
INPUT/OUTPUT
0, 2, 4, 6, 8
1, 3, 5, 7
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
description (continued)
In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR)
output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example,
if 1ODD/EVEN
1ERR is low, indicating a parity error.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16657 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16657 is characterized for operation from –40°C to 85°C.
is high (odd parity selected), 1P ARITY is high, and there are three high bits on the 1B bus, then
FUNCTION TABLE
(each 8-bit section)
NUMBER OF A OR B
INPUTS THAT ARE HIGH
Don’t care H X X Z Z Z
OE
INPUTS
T/R
ODD/EVEN
L H H H Z Transmit
L HL L Z Transmit
L LH H H Receive
L LH L L Receive
L LL H L Receive
L LL L H Receive
L H H L Z Transmit
L HL H Z Transmit
L LH H L Receive
L LH L H Receive
L LL H H Receive
L LL L L Receive
INPUT/OUTPUT
PARITY
ERR
OUTPUTS
OUTPUT MODE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
logic symbol
†
1
1OE
1T/R
1ODD/EVEN
2OE
2T/R
2ODD/EVEN
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
55
28
29
30
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
G3
3 EN1/3G5 [REC]
3 EN2 [XMIT]
N4
G8
8 EN6/8G10 [REC]
8 EN7 [XMIT]
N9
6
1
12
, 2
4
4
, 1
1
12k7
2k
9, 7
9, 6
Z11
11
•
•
•
18
Z21
21
•
•
•
28
1
10
52
1B1
51
1B2
49
1B3
48
1B4
47
1B5
45
1B6
44
1B7
43
1B8
54
1PARITY
5
42
41
40
38
37
36
34
33
31
26
3
1ERR
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2PARITY
2ERR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
logic diagram (positive logic)
T/R
OE
A1
B1
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
ODD/EVEN
4
PARITY
ERR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16657 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT16657 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16657 SN74ABT16657
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT16657, SN74ABT16657
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
V
V
V
GND
A
V
CC
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16657 SN74ABT16657
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
Control inputs
I
A or B ports
‡
I
OZH
‡
I
OZL
I
off
I
CEX
§
I
O
I
A or B ports
CC
¶
∆I
CC
C
Control inputs VI = 2.5 V or 0.5 V 3 pF
i
C
A or B ports VO = 2.5 V or 0.5 V 9 pF
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±450 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
OZH
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 24 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
=
or
I
CC
Outputs high 50 50 50 µA
Outputs high 2 2 2
Outputs low 36 36 36
Outputs disabled 2 2 2
±1 ±1 ±1
±100 ±100 ±100
50 50 50 µA
µ
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
A or B
B or A
ns
A
PARITY
ns
ODD/EVEN
PARITY, ERR
ns
B
ERR
ns
PARITY
ERR
ns
OE
A or B
ns
OE
A or B
ns
OE
PARITY, ERR
ns
OE
PARITY, ERR
ns
SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1.5 2.5 3.3 1.5 4.2 1.5 4.1
2 3.1 3.9 2 4.5 2 4.3
2 4.6 5.4 2 7 2 6.7
2 4.3 5.1 2 6.5 2 6.1
2 4.6 5.4 2 7 2 6.7
2 4.3 5.1 2 6.5 2 6.1
2 4.6 5.4 2 7 2 6.7
2 4.3 5.1 2 6.5 2 6.1
2 4.6 5.4 2 7 2 6.7
2 4.3 5.1 2 6.5 2 6.1
2 3.9 4.9 2 5.8 2 5.6
2.5 4.3 5.1 2.5 6.2 2.5 6
2 3.6 4.5 2 5.5 2 5.4
1.5 3 3.8 1.5 4.7 1.5 4.3
2 4 4.9 2 5.8 2 5.6
2.5 4.1 5.1 2.5 6.2 2.5 6
1 3.5 4.5 1 5.5 1 5.4
1.5 3 3.8 1.5 4.7 1.5 4.3
SN54ABT16657 SN74ABT16657
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ABT16657, SN74ABT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
GND
OH
OL
OH
OL
Open
3 V
0 V
Timing Input
Data Input
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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