SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
(Output Ground Bounce)
OLP
< 1 V at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
The ’ABT16652 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. These devices can be used as
two 8-bit transceivers or one 16-bit transceiver.
Output-enable (OEAB and OEBA
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT16652.
) inputs are
SN54ABT16652 . . . WD PACKAGE
SN74ABT16652 . . . DL PACKAGE
1OEAB
1CLKAB
2CLKAB
2OEAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control inputs. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA
. In this configuration, each output reinforces its input. When all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16652, SN74ABT16652
OPERATION OR FUNCTION
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN54ABT16652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB
†
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
OEBA
L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
H H ↑↑X
L X H or L ↑ X X Unspecified
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output
CLKAB CLKBA SAB SBA A1–A8 B1–B8
‡
X Input Output Store A in both registers
DATA I/O
‡
†
‡
Input Hold A, store B
Store A, hold B
Stored A data to B bus and
stored B data to A bus
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
BUS A
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS A
OEAB OEBA
HH
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
OEAB
X
L
L
BUS A
OEBA
CLKAB CLKBAXSABXSBA
H
X
H
STORAGE FROM
A, B, OR A AND B
BUS B
↑
XX
↑
X
↑↑
X
X
X
Figure 1. Bus-Management Functions
BUS A
OEAB OEBA
H L H or L H H
CLKAB CLKBA SAB SBA
H or L
TRANSFER STORED DA TA
TO A AND/OR B
BUS B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol
†
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN1 [BA]
EN2 [AB]
C3
G4
C5
G6
EN7 [BA]
EN8 [AB]
C9
G10
C11
G12
≥ 1
1
5D
16
≥ 1
7
11D
12
112
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
3D
441
≥ 1
6
2
10
9D
1
10
≥ 1
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
2OEBA
56
1
55
54
2
3
5
29
One of Eight Channels
1D
C1
To Seven Other Channels
C1
1D
52
1B1
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
28
30
31
27
26
15
One of Eight Channels
1D
C1
To Seven Other Channels
C1
1D
42
2B1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT16652, SN74ABT16652
UNIT
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16652 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT16652 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16652 SN74ABT16652
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
0 V
CC
V
†
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
µ
I
CC
,
ICC
µ
V
CC
¶
Data inputs
,
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16652 SN74ABT16652
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
Control
I
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
inputs
A or B ports
‡
‡
§
A or B ports
p
CC
Control
inputs
Control
i
inputs
A or B ports VO = 2.5 V or 0.5 V 8 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
V
= 5.5 V, V
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 4 pF
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
= V
or GND
Outputs high 50 50 50 µA
Outputs high 2 2 2
Outputs low 32 32 32
Outputs disabled 2 2 2
Outputs enabled 50 50 50
Outputs disabled 50 50 50
±1 ±1 ±1
±20 ±20 ±20
50 50 50
A
mA
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16652
VCC = 5 V,
f
clock
t
w
t
su
t
h
TA = 25°C
MIN MAX
Clock frequency 0 125 0 125 MHz
Pulse duration, CLK high or low 4.3 4.3 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3.5 4 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 0.5 0.5 ns
MIN MAX
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16652
VCC = 5 V,
f
clock
t
w
t
su
t
h
TA = 25°C
MIN MAX
Clock frequency 0 125 0 125 MHz
Pulse duration, CLK high or low 4.3 4.3 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 ns
MIN MAX
UNIT
UNIT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK
B or A
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OEBA
A
ns
OEBA
A
ns
OEAB
B
ns
OEAB
B
ns
CLK
B or A
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OEBA
A
ns
OEBA
A
ns
OEAB
B
ns
OEAB
B
ns
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN54ABT16652
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
1.5 3.1 4 1 5
1.5 3.2 4.1 1 5
1 2.3 3.2 0.6 4
1 3 4.1 0.6 4.9
1 2.9 4.3 0.6 5.3
1 3.1 4.6 0.6 5.3
1 2.8 4.1 0.6 5.2
1.5 3.1 4.4 1 5.4
1.5 3.4 4.7 0.8 5.3
1.5 2.7 4 1 5.3
1 2.6 3.6 0.8 4.7
1.5 2.8 4.5 1 5
2 4.2 5.9 1 6.4
1.5 3.4 4.9 1 5.9
MIN MAX
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN74ABT16652
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
1.5 3.1 4 1.5 4.9
1.5 3.2 4.1 1.5 4.7
1 2.3 3.2 1 3.9
1 3 4.1 1 4.6
1 2.9 4.3 1 5
1 3.1 4.3 1 5
1 2.8 4.1 1 5
1.5 3.1 4.4 1.5 5.3
1.5 3.4 4.4 1.5 4.9
1.5 2.7 3.6 1.5 4
1 2.6 3.6 1 4.2
1.5 2.8 3.9 1.5 4.6
2 4.2 5.5 2 5.9
1.5 3.4 4.5 1.5 5.2
MIN MAX
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
10
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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