Texas Instruments SN74ABT16540ADGGR, SN74ABT16540ADGVR, SN74ABT16540ADL, SN74ABT16540ADLR Datasheet

SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The SN54ABT16540 and SN74ABT16540A are
inverting 16-bit buffers/drivers composed of two
8-bit sections with separate output-enable gates.
These buffers and bus drivers provide a
high-performance bus interface for wide data
paths.

The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1

or OE2) input is high, all corresponding

outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16540 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16540A is characterized for operation from –40°C to 85°C.

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

SN54ABT16540 . . . WD PACKAGE

SN74ABT16540A . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

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24

48
47
46
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32
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29
28
27
26
25

1OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6

GND

1Y7
1Y8
2Y1
2Y2

GND

2Y3
2Y4

V

CC

2Y5
2Y6

GND

2Y7
2Y8

2OE1

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V

CC

2A5
2A6
GND
2A7
2A8
2OE2

SN54ABT16540, SN74ABT16540A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

OE1 OE2

A

Y

L L L H
L LH L
H XX Z
X H X Z

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

47

1A1

1

1Y1

2

48

46

1A2 1Y2

3

24
25

44

1A3 1Y3

5

43

1A4 1Y4

6

41

1A5 1Y5

8

40

1A6

1Y6

9

38

1A7 1Y7

11

37

1A8 1Y8

12

36

2A1 2Y1

13

35

2A2 2Y2

14

33

2A3 2Y3

16

32

2A4 2Y4

17

30

2A5

2Y5

19

29

2A6 2Y6

20

27

2A7 2Y7

22

26

2A8 2Y8

23

1OE1
1OE2
2OE1
2OE2

&

&

11

12

EN1

EN2

logic diagram (positive logic)

1OE1
1OE2

2OE1
2OE2

1A1 1Y1

2Y1

2A1

To Seven Other Channels To Seven Other Channels

1
48

47

24
25

36

2

13