Datasheet SN74ABT16500BDGGR, SN74ABT16500BDL, SN74ABT16500BDLR Datasheet (Texas Instruments)
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Flow-Through Architecture Optimizes PCB
Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB
and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB
is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the high-to-low transition of CLKAB. OEAB is
active-high. When OEAB is high, the outputs are
active. When OEAB is low, the outputs are in the
high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
SN54ABT16500B . . . WD PACKAGE
SN74ABT16500B . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The SN54ABT16500B is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16500B is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L X X X Z
H HXLL
H HXHH
H L ↓ LL
H L ↓ HH
H LHXB
0
‡
H L L X B
0
§
†
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA
, LEBA, and CLKBA.
‡
Output level before the indicated steady-state input
conditions were established
§
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
A2
5
EN1
1
OEAB
2C3
3D
3
A1 B1
54
A14
20
A15
21
A16
23
A17
24
A8
13
A9
14
A10
15
A11
16
A12
17
A3
6
A4
8
A5
9
A6
10
A7
12
B13
38
B14
37
B15
36
B16
34
B17
33
B18
31
6D
4
A18
26
B8
44
B9
43
B10
42
B11
41
B12
40
B3
51
B4
49
B5
48
B6
47
B7
45
B2
52
C6
28
LEBA
G5
30
EN4
27
C3
2
LEAB
G2
55
5C6
CLKBA
OEBA
CLKAB
11
1
A13
19
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
54
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16500B 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16500B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABT16500B SN74ABT16500B
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16500B SN74ABT16500B
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
V
OH
IOH = –24 mA 2 2
V
V
CC
=
4.5 V
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
VOLV
CC
= 4.5
V
IOL = 64 mA 0.55* 0.55
V
V
hys
100 mV
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high 50 50 50 µA
Control
inputs
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1
I
I
A or B ports
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
±20 ±20 ±20
µ
A
I
O
‡
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
I
OZPU
§
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
or OE = X
±50 ±50 ±50 µA
I
OZPD
§
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
or OE = X
±50 ±50 ±50 µA
I
OZH
¶
VCC = 2.1 V to 5.5 V, VO = 2.7 V,
OE
≥ 2 V, OE ≤ 0.8 V
#
10 10 10 µA
I
OZL
¶
VCC = 2.1 V to 5.5 V, VO = 0.5 V,
OE
≥ 2 V, OE ≤ 0.8 V
#
–10 –10 –10 µA
=
Outputs high 3 3 3
I
CC
A or B ports
V
CC
= 5.5 V,
IO = 0,
Outputs low 36 36 36
mA
VI = VCC or GND
Outputs disabled 3 3 3
∆I
CC
||
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
50 50 50 µA
C
i
Control
inputs
VI = 2.5 V or 0.5 V 3 pF
C
io
A or B ports VO = 2.5 V or 0.5 V 9 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§
This parameter is characterized, but not production tested.
¶
The parameters I
OZH
and I
OZL
include the input leakage current.
#
For VCC between 2.1 V and 4 V , OE should be less than or equal to 0.5 V to ensure a low state.
||
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16500B SN74ABT16500B
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 0 150 0 150 MHz
LEAB or LEBA high 2.5 2.5
t
w
†
Pul
se duration
CLKAB
or CLKBA high or low
3 3
ns
A before CLKAB↓
3 3
p
B before CLKBA↓
3 3
tsuSetup time
CLK high
1 1
ns
A before LEAB↓ or B before LEBA↓
CLK low
2.5 2.5
A after CLKAB↓ or B after CLKBA↓
0 0
thHold time
A after LEAB↓ or B after LEBA↓ 2 2
ns
†
This parameter is characterized, but not production tested.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABT16500B SN74ABT16500B
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
f
max
150 200 150 150 MHz
t
PLH
1 2.5 3.6 1 4.2 1 4
t
PHL
A or B
B or A
1 3.2 4.5 1 5.1 1 4.9
ns
t
PLH
1 3.2 4.5 1 5.6 1 5
t
PHL
LEAB
or
LEBA
B or A
1 3.4 4.5 1 5.4 1 5
ns
t
PLH
1 3.5 4.7 1 5.4 1 5.3
t
PHL
CLKAB
or
CLKBA
B or A
1 3.5 4.7 1 5.4 1 5.3
ns
t
PZH
1 3.4 4.6 1 5.3 1 5.1
t
PZL
OEAB
or
OEBA
B or A
1.5 3.8 4.7 1.5 5.6 1.5 5.4
ns
t
PHZ
1.5 4.5 5.7 1.5 6.9 1.5 6.5
t
PLZ
OEAB
or
OEBA
B or A
1.4 3.4 4.7 1.4 5.8 1.4 5.4
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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