Texas Instruments SN74ABT162825DL, SN74ABT162825DLR Datasheet

SN54ABT162825, SN74ABT162825

18-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS474C – JUNE 1994 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings

description

The ’ABT162825 are 18-bit buffers and line
drivers designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices
provide true data, and can be used as two 9-bit
buffers or one 18-bit buffer.

The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1

or OE2) input is high, all nine affected

outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to

reduce overshoot and undershoot.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT162825 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162825 is characterized for operation from –40°C to 85°C.

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABT162825 . . . WD PACKAGE

SN74ABT162825 . . . DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6
1Y7

GND

1Y8

1Y9
GND
GND

2Y1

2Y2
GND

2Y3

2Y4

2Y5

V

CC

2Y6

2Y7
GND

2Y8

2Y9

2OE1

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V

CC

2A6
2A7
GND
2A8
2A9
2OE2

SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS474C – JUNE 1994 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each 9-bit buffer)

INPUTS

OUTPUT

OE1

OE2 A

Y

L L L L
L LH H
H XX Z
X H X Z

logic symbol

†

55

1A1 1Y1

2

54

1A2 1Y2

3

52

1A3

1Y3

5

51

1A4 1Y4

6

49

1A5 1Y5

8

48

1A6 1Y6

9

47

1A7 1Y7

10

45

1A8 1Y8

12

44

1A9 1Y9

13

1

41

2A1

2Y1

16

40

2A2 2Y2

17

38

2A3 2Y3

19

37

2A4 2Y4

20

36

2A5 2Y5

21

34

2A6 2Y6

23

33

2A7 2Y7

24

31

2A8 2Y8

26

30

2A9

2Y9

27

2

1
56

28
29

1OE1
1OE2
2OE1

2OE2

&

&

EN1

EN2

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

logic diagram (positive logic)

1A1 1Y1

2

1

55

56

To Eight Other Channels

2A1 2Y1

16

28

41

29

To Eight Other Channels

1OE1
1OE2

2OE1
2OE2

SN54ABT162825, SN74ABT162825

18-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS474C – JUNE 1994 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT162825 SN74ABT162825

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –12 –12 mA

I

OL

Low-level output current 12 12 mA

p

Control inputs 9 9

∆t/∆vInput transition rise or fall rate

Data inputs 10 10

ns/V

∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

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design phase of development. Characteristic data and other
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change or discontinue these products without notice.