Datasheet SN74ABT16245ADGGR, SN74ABT16245ADGVR, SN74ABT16245ADL, SN74ABT16245ADLR, SNJ54ABT16245AWD Datasheet (Texas Instruments)

SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
D
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up and Power Down
D
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Latch-Up Performance Exceeds 500 mA Per JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Thin Very Small-Outline (DGV), Shrink Small-Outline (DL), and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic (WD) Flat Package Using 25-mil Center-to-Center Spacings
description
SN54ABT16245A . . . WD PACKAGE
SN74ABT16245A . . . DGG, DGV, OR DL PACKAGE
1DIR
1B1 1B2
GND
1B3 1B4
V
CC
1B5 1B6
GND
1B7 1B8 2B1 2B2
GND
2B3 2B4
V
CC
2B5 2B6
GND
2B7 2B8
2DIR
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE 1A1 1A2 GND 1A3 1A4 V
CC
1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V
CC
2A5 2A6 GND 2A7 2A8 2OE
The ’ABT16245A devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE
) input can be used to disable the device so that the buses are effectively
isolated. When V
However, to ensure the high-impedance state above 2.1 V, OE
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16245A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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1
SN54ABT16245A, SN74ABT16245A
OPERATION
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
FUNCTION TABLE
(each 8-bit section)
INPUTS
DIR
OE
L L B data to A bus L H A data to B bus
H X Isolation
logic symbol
1OE
1DIR
2OE
2DIR
1A1
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
48 1
25 24
47
46 44 43 41 40 38 37 36
35 33 32 30 29 27 26
G3 3 EN1 [BA]
3 EN2 [AB] G6 6 EN4 [BA]
6 EN5 [AB]
1
4
2
1B1
2
5
11 12 13
14 16 17 19 20 22 23
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6 1B7 1B8 2B1
2B2 2B3 2B4 2B5 2B6 2B7 2B8
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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UNIT
logic diagram (positive logic)
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
1DIR
1A1
1
47
To Seven Other Channels
48
1OE
2
1B1
2DIR
2A1
24
36
To Seven Other Channels
25
13
2OE
2B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16245A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16245A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16245A SN74ABT16245A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
t/v Input transition rise or fall rate Outputs enabled 10 10 ns/Vt/V
T
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 0 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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CC
0 V
CC
V
3
SN54ABT16245A, SN74ABT16245A
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
A
V
CC
D
,
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54ABT16245A SN74ABT16245A
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
Control
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
I
C C
* On products compliant to MIL-PRF-38535, this parameter does not apply. ** On products compliant to MIL-PRF-38535, this parameter is not production tested.
All typical values are at VCC = 5 V.
The parameters I
§
This limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
inputs A or B ports
A or B ports
ata inputs
#
CC
Control inputs
Control
i
inputs A or B ports VO = 2.5 V or 0.5 V 6 pF
o
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 VCC = 2.1 V to 5.5 V,
VI = VCC or GND VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE VCC = 0, VI or VO 4.5 V ±100 ±100 µA VCC = 5.5 V,
VO = 5.5 V VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
=
= 5.5 V, IO = 0, VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3 pF
OZH
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2 IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 IOL = 64 mA 0.55* 0.55
100 mV
±20* ±100 ±20
= X
= X
2 V
2 V
Outputs high 50 50 50 µA
Outputs high 2 2 2 Outputs low 32 32 32 Outputs disabled 2 2 2
Outputs enabled 2 1.5 2
Outputs disabled 0.05 1 0.05
±50** ±50** ±50 µA
±50** ±50** ±50 µA
§
10
§
–10
1.5 1.5 1.5
10 10
–10 –10
µ
§
µA
§
µA
mA
mA
4
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A or B
B or A
ns
OE
B or A
ns
OE
B or A
ns
A or B
B or A
ns
OE
B or A
ns
OE
B or A
ns
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
TO
(OUTPUT)
SN54ABT16245A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
0.5 2.2 3.4 0.5 4
0.5 2.3 3.8 0.5 4.6
0.8 3.6 5.2 0.8 5.5
0.9 3.7 6.1 0.1 7.3
1.3 4.4 5.8 1.3 6.3
1.4 3.3 4.7 1.4 5.3
SN74ABT16245A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
1 2.2 3.4 1 3.9 1 2.3 3.7 1 4.2 1 3.6 5.2 1 6.3 1 3.7 5.4 1 6.4 2 4.4 5.8 2 6.3
1.5 3.3 4.7 1.5 5.2
MIN MAX
MIN MAX
UNIT
UNIT
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5
SN54ABT16245A, SN74ABT16245A 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS300E – MARCH 1994 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
500
t
w
1.5 V
500
1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
1.5 V1.5 V
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
t
VOL + 0.3 V
t
VOH – 0.3 V
PLZ
PHZ
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright 1999, Texas Instruments Incorporated
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