Datasheet SN74ABT126D, SN74ABT126DBLE, SN74ABT126DBR, SN74ABT126DR, SN74ABT126N Datasheet (Texas Instruments)

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SN54ABT126, SN74ABT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS183D – FEBRUARY 1991 – REVISED JANUARY 1999
D
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Typical V at V
D
High-Impedance State During Power Up
= 5 V, TA = 25°C
CC
(Output Ground Bounce) <1 V
OLP
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Latch-Up Performance Exceeds 500 mA Per JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs
description
The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
When V in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V , OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
is between 0 and 2.1 V, the device is
CC
SN54ABT126 ...J PACKAGE
SN74ABT126 . . . D, DB, OR N PACKAGE
SN54ABT126 . . . FK PACKAGE
1Y
NC
2OE
NC
2A
NC – No internal connection
(TOP VIEW)
1OE
2OE
GND
1
1A
2
1Y
3 4
2A
5
2Y
6 7
(TOP VIEW)
1A
3212019
4 5 6 7 8
910111213
2Y
1OE
GND
14 13 12 11 10
NC
NC
9 8
CC
V
3Y
V
CC
4OE 4A 4Y 3OE 3A 3Y
4OE
18 17 16 15 14
3A
4A NC 4Y NC 3OE
The SN54ABT126 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
INPUTS
OE A
H H H H LL
LXZ
OUTPUT
Y
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D – FEBRUARY 1991 – REVISED JANUARY 1999
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
1OE
1A
2OE
2A
3OE
3A
4OE
4A
1 2 4 5 10 9 13 12
EN
1
logic diagram (positive logic)
1
1OE
2
1A 1Y
4
2OE
3
3OE
3A 3Y
4OE
10
9
13
3
1Y
6
2Y
8
3Y
11
4Y
8
5
2A 2Y
Pin numbers shown are for the D, DB, J, and N packages.
6
12
4A 4Y
11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high or power-off state, V Current into any output in the low state, I
Input clamp current, I Output clamp current, I Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT126 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
SN74ABT126 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
V
V
V
I
V
CC
GND
I
O
SN54ABT126, SN74ABT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS183D – FEBRUARY 1991 – REVISED JANUARY 1999
recommended operating conditions (see Note 3)
SN54ABT126 SN74ABT126
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
t/v Input transition rise or fall rate 10 10 ns/Vt/V
T
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
V
V I
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
C C
* On products compliant to MIL-PRF-38535, this parameter does not apply. †
All typical values are at VCC = 5 V.
For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Supply voltage 4.5 5.5 4.5 5.5 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 0 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
IK
OH
OL
hys
§
CC
i o
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3
= 4.5
CC
= 4.5
CC
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 0.8 V 10 10 10 µA VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 0.8 V –10 –10 –10 µA VCC = 0, VI or VO 4.5 V ±100 ±100 µA VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
VCC = 5.5 V, IO = 0,
=
or
VCC = 5.5 V,
p
ne input at 3.4 V,
Other inputs at VCC or GND VI = 2.5 V or 0.5 V 3 pF VO = 2.5 V or 0.5 V 7 pF
, literature number SCBA004.
TA = 25°C SN54ABT126 SN74ABT126
MIN TYP†MAX MIN MAX MIN MAX
IOH = –24 mA 2 2 IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 IOL = 64 mA 0.55* 0.55
100 mV
Outputs high 1 250 250 250 µA Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 µA
Outputs enabled 1.5 1.5 1.5 mA Outputs disabled 50 50 50 µA
±50 ±50 ±50 µA ±50 ±50 ±50 µA
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54ABT126, SN74ABT126
(INPUT)
(OUTPUT)
A
Y
ns
OE
Y
ns
OE
Y
ns
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D – FEBRUARY 1991 – REVISED JANUARY 1999
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 1)
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
NOTE 4: Limits may vary among suppliers.
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1 2.9 4.9 1 7.3 1 6.3 1 2.5 5.1 1 5.9 1 5.7 1 4.4 5.8 1 5.3 1 6.5 1 4.4 5.9 1 6.4 1 6.5 1 3 5.7 1 6.9 1 6.8 1 3 5.8 1 7.2 1 6.7
SN54ABT126 SN74ABT126
UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS183D – FEBRUARY 1991 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
500
t
w
1.5 V
500
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
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