Datasheet SN74ABT125D, SN74ABT125DBLE, SN74ABT125DBR, SN74ABT125DR, SN74ABT125N Datasheet (Texas Instruments)

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (N)
and Ceramic (J) DIPs

description

The ’ABT125 quadruple bus buffer gates feature
independent line drivers with 3-state outputs.
Each output is disabled when the associated
output-enable (OE

When VCC is between 0 and 2.1 V, the device is
in the high-impedance state during power up or
power down. However, to ensure the
high-impedance state above 2.1 V , OE should be
tied to V

through a pullup resistor; the minimum

CC

value of the resistor is determined by the
current-sinking capability of the driver.

) input is high.

SN54ABT125 ...J OR W PACKAGE

SN74ABT125 . . . D, DB, N, OR PW PACKAGE

SN54ABT125 . . . FK PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

(TOP VIEW)

1OE

1A
1Y

2OE

2A
2Y

GND

(TOP VIEW)

3212019

4
5
6
7
8

910111213

1
2
3
4
5
6
7

1A

2Y

1OE

GND

14
13
12
11
10

NC

NC

V

CC

4OE
4A
4Y
3OE
3A

9

3Y

8

CC

V

4OE

18

4A

17

NC

16

4Y

15

NC

14

3OE

3Y

3A

The SN54ABT125 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT125 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

INPUTS

OE A

L H H
L LL

H X Z

OUTPUT

Y

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

†

1OE

1A

2OE

2A

3OE

3A

4OE

4A

1
2

4
5

10
9

13
12

EN

1

logic diagram (positive logic)

1

1OE

2

1A 1Y

4

2OE

3

3OE

3A 3Y

4OE

10

9

13

3

1Y

6

2Y

8

3Y

11

4Y

8

5

2A 2Y

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

6

12

4A 4Y

11

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT125 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

SN74ABT125 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

‡

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

recommended operating conditions (see Note 3)

SN54ABT125 SN74ABT125

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 10 10 ns/V
∆t/∆V

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

CC

0 V

CC

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT125, SN74ABT125

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

VOLV

V

V

V

CC

#

,

QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT125 SN74ABT125

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

V

hys

I

I

‡

I

OZPU

‡

I

OZPD

I

OZH

I

OZL

I

off

I

CEX

§

I

O

I

CC

Data

∆I

C
C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This limit may vary among suppliers.

#

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

inputs

CC

Control
inputs

i
o

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA
VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –200

=

= 5.5 V,
IO = 0,
VI = VCC or GND

VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 7 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

Outputs high 50 50 50 µA

¶

–50 –200
Outputs high 1 250 250 250 µA
Outputs low 24 30 30 30 mA
Outputs disabled 0.5 250 250 250 µA

Outputs enabled 1.5 1.5 1.5

Outputs disabled 0.05 0.05 0.05

1.5 1.5 1.5

¶

–50 –200

¶

mA

mA

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(INPUT)

(OUTPUT)

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

PARAMETER

†

t

PLH

†

t

PHL

†

t

PZH

†

t

PZL

t

PHZ

†

t

PLZ

†

This limit may vary among suppliers.

FROM

TO

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

1 3.2 4.6 1 6 1 4.9
1 2.5 4.6 1 6.2 1 4.9
1 3.6 5 1 6 1 5.9
1 2.5 6.2 1 7.5 1 6.8
1 3.8 5.4 1 6.3 1 6.2
1 3.3 5.3 1 6.5 1 6.2

SN54ABT125 SN74ABT125

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCBS182E – FEBRUARY 1997 – REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

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