Texas Instruments SN 65 MLVD 202 A, SN 65 MLVD 200 A INSTALLATION INSTRUCTIONS

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MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

FEATURES DESCRIPTION

• Low-Voltage Differential 30- Ω to 55- Ω Line

Drivers and Receivers for Signaling Rates
Up to 100 Mbps, Clock Frequencies up to
50 MHz

• Type-1 Receivers Incorporate 25 mV of

Hysteresis (200A, 202A)

• Type-2 Receivers Provide an Offset(100 mV)

Threshold to Detect Open-Circuit and Idle-Bus
Conditions (204A, 205A)

• Meets or Exceeds the M-LVDS Standard

TIA/EIA-899 for Multipoint Data Interchange

• Power Up/Down Glitch Free

• Controlled Driver Output Voltage Transition

Times for Improved Signal Quality

• –1 V to 3.4 V Common-Mode Voltage Range

Allows Data Transfer With 2 V of Ground
Noise

• Bus Pins High Impedance When Disabled or

V

≤ 1.5 V

CC

• 200-Mbps Devices Available (SN65MLVD201,

203, 206, 207)

• Bus Pin ESD Protection Exceeds 8 kV

• Package in 8-Pin SOIC (200A, 204A) and

14-Pin SOIC (202A, 205A)

• Improved Alternatives to the SN65MLVD200,

202, 204, and 205

APPLICATIONS

• Low-Power High-Speed Short-Reach

Alternative to TIA/EIA-485

• Backplane or Cabled Multipoint Data and

Clock Transmission

• Cellular Base Stations

• Central-Office Switches

• Network Switches and Routers

(1) The signaling rate of a line, is the number of voltage

transitions that are made per second expressed in the nits
bps (bits per second).

SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

(1)

The SN65MLVD200A, 202A, 204A, and 205A are
multipoint-low-voltage differential (M-LVDS) line
drivers and receivers, which are optimized to operate
at signaling rates up to 100 Mbps. All parts comply
with the multipoint low-voltage differential signaling
(M-LVDS) standard TIA/EIA-899. These circuits are
similar to their TIA/EIA-644 standard compliant LVDS
counterparts, with added features to address
multipoint applications. The driver output has been
designed to support multipoint buses presenting
loads as low as 30 Ω , and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.

These devices have Type-1 and Type-2 receivers
that detect the bus state with as little as 50 mV of
differential input voltage over a common-mode
voltage range of –1 V to 3.4 V. The Type-1 receivers
exhibit 25 mV of differential input voltage hysteresis
to prevent output oscillations with slowly changing
signals or loss of input. Type-2 receivers include an
offset threshold to provide a known output state
under open-circuit, idle-bus, and other fault
conditions.

The SN65MLVD200A, 202A, 204A, and 205A have
enhancements over their predecessors. Improved
features include better controlled slew rate on the
driver output to help minimize reflections while
improving overall signal integrity (SI) resulting in
better jitter performance. Additionally, 8-kV ESD
protection on the bus pins for more robustness. The
same footprint definition was maintained making for
an easy drop-in replacement for a system
performance upgrade.

The devices are characterized for operation from
–40 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2003–TBD, Texas Instruments Incorporated

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4

3

1

2

DE

D

RE

R

6
7

A
B

LOGIC DIAGRAM (POSITIVE LOGIC)

5
4

2

3

DE

D

RE

R

12
11

A
B

10

9

Y
Z

SN65MLVD202A, SN65MLVD205A

SN65MLVD200A, SN65MLVD204A

SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

SN65MLVD200AD SN75176 Type 1 MF200A
SM65MLVD202AD SN75ALS180 Type 1 MLVD202A
SN65MLVD204AD SN75176 Type 2 MF204A
SM65MLVD205AD SN75ALS180 Type 2 MLVD205A

(1) Available tape and reeled. To order a tape and reeled part, add the suffix R to the part number (e.g., SN65MLVD200ADR).

(1)

FOOTPRINT RECEIVER TYPE PACKAGE MARKING

PACKAGE DISSIPATION RATINGS

PACKAGE

D(8) 532 mW 4.6 mW/ ° C 254 mW

D(14) 940 mW 8.2 mW/ ° C 450 mw

POWER RATING ABOVE TA= 25°C POWER RATING

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

Supply voltage range

Input voltage range A, B (200A, 204A) –1.8 V to 4 V

Output voltage range

Electrostatic discharge All pins ± 4 kV

Continuous power dissipation See Dissipation Rating Table
Storage temperature range –65 ° C to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

2

(2)

, V

CC

D, DE, RE –0.5 V to 4 V

A, B (202A, 205A) –4 V to 6 V
R –0.3 V to 4 V
Y, Z, A, or B –1.8 V to 4 V

Human Body Model

Charged-Device Model

TA≤ 25 ° C DERATING FACTOR TA= 85 ° C

(1)

SN65MLVD200A,

202A, 204A, and 205A

–0.5 V to 4 V

(3)

A, B, Y, and Z ± 8 kV

(4)

All pins ± 1500 V

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SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

V
V
V

|V
R
1/t
T

DEVICE ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

I

P

(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.

Supply voltage 3 3.3 3.6 V

CC

High-level input voltage 2 V

IH

Low-level input voltage GND 0.8 V

IL

Voltage at any bus terminal VA, VB,VYor V

| Magnitude of differential input voltage 0.05 V

ID

Differential load resistance 30 50 Ω

L

Signaling rate 100 Mbps

UI

Operating free-air temperature –40 85 ° C

A

Z

–1.4 3.8 V

PARAMETER TEST CONDITIONS MIN MAX UNIT

Driver only RE and DE at VCC, RL= 50 Ω , All others open 13 22

Supply current mA

CC

Both disabled RE at VCC, DE at 0 V, RL= No Load, All others open 1 4
Both enabled RE at 0 V, DE at VCC, RL= 50 Ω , All others open 16 24
Receiver only RE at 0 V, DE at 0 V, All others open 4 13

Device power dissipation 94 mW

D

RL= 50 Ω , Input to D is a 50-MHz 50% duty cycle square
wave, DE = high, RE = low, TA= 85 ° C

SLLS573 – DECEMBER 2003

CC

CC

(

(1)

TYP

)

V

V

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SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

(1)

–50 50 mV

SS

|V

| or

AB

|V

YZ

∆ |V
∆ |V

V

OS(SS)

∆ V

OS(SS)

V

OS(PP)

V

Y(OC)

V

A(OC)

V

Z(OC)

V

B(OC)

V

P(H)

V

P(L)

I

IH

I

IL

Differential output voltage magnitude 480 650 mV

|

| or Change in differential output voltage magnitude

AB

| between logic states

YZ

Steady-state common-mode output voltage 0.8 1.2 V
Change in steady-state common-mode output

voltage between logic states
Peak-to-peak common-mode output voltage 150 mV

or

Maximum steady-state open-circuit output voltage 0 2.4 V

or

Maximum steady-state open-circuit output voltage 0 2.4 V
Voltage overshoot, low-to-high level output 1.2 V

Voltage overshoot, high-to-low level output –0.2 V
High-level input current (D, DE) VIH= 2 V to V
Low-level input current (D, DE) VIL= GND to 0.8 V 0 10 µA

PARAMETER TEST CONDITIONS MIN

See Figure 2

See Figure 3 –50 50 mV

See Figure 7

See Figure 5

CC

|IOS| Differential short-circuit output current magnitude See Figure 4 24 mA
I

OZ

I

O(OFF)

CYor C

C

YZ

C

Y/Z

High-impedance state output current (driver only) –15 10 µA

Power-off output current –10 10 µA

–1.4 V ≤ (V
Other output = 1.2 V

–1.4 V ≤ (V
output = 1.2 V, 0 V ≤ VCC≤ 1.5 V

VI= 0.4 sin(30E6 π t) + 0.5 V,

Output capacitance Other input at 1.2 V, driver 3 pF

Z

Differential output capacitance 2.5 pF
Output capacitance balance, (C

) 0.99 1.01

Y/CZ

disabled
V

= 0.4 sin(30E6 π t) V,

AB

Driver disabled

or VZ) ≤ 3.8 V,

Y

or VZ) ≤ 3.8 V, Other

Y

(3)

(3)

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)

(2)

TYP

MAX UNIT

0 10 µA

V

SS

V

4

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SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

RECEIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

V

IT+

V

IT-

V

HYS

V

OH

V

OL

I

IH

I

IL

I

OZ

CAor VI= 0.4 sin(30E6 π t) + 0.5 V,
C

B

C

AB

C

A/B

Positive-going differential input voltage threshold mV

Negative-going differential input voltage threshold mV

Differential input voltage hysteresis, (V

– V

IT+

High-level output voltage IOH= –8 mA 2.4 V
Low-level output voltage IOL= 8 mA 0.4 V
High-level input current ( RE) VIH= 2 V to V
Low-level input current ( RE) VIL= GND to 0.8 V –10 0 µA
High-impedance output current VO= 0 V or 3.6 V –10 15 µA

Input capacitance 3 pF
Differential input capacitance V

Input capacitance balance, (C

) 0.99 1.01

A/CB

(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)

Type 1 50
Type 2 150
Type 1 –50
Type 2 50
Type 1 25

) mV

IT–

Type 2 0

See Figure 9, Table 1 and Table
2

CC

Other input at 1.2 V

= 0.4 sin(30E6 π t) V

AB

SLLS573 – DECEMBER 2003

(1)

MAX UNIT

–10 0 µA

(2)

(2)

2.5 pF

BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

I

I

I

I

I

I

C

C

C

C

Receiver or transceiver with driver disabled

A

input current

Receiver or transceiver with driver disabled

B

input current

Receiver or transceiver with driver disabled

AB

differential input current (IA– IB)

Receiver or transceiver power-off input current VA= 0 V or 2.4 V, VB= 1.2 V, 0 V ≤ VCC≤ 1.5 V –20 20 µA

A(OFF)

Receiver or transceiver power-off input current VB= 0 V or 2.4 V, VA= 1.2 V, 0 V ≤ VCC≤ 1.5 V –20 20 µA

B(OFF)

Receiver input or transceiver power-off

AB(OFF)

differential input current (IA– IB)
Transceiver with driver disabled input

A

capacitance
Transceiver with driver disabled input

B

capacitance
Transceiver with driver disabled differential

AB

input capacitance
Transceiver with driver disabled input

A/B

capacitance balance, (CA/CB)

(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)

VA= 3.8 V, VB= 1.2 V, 0 32
VA= 0 V or 2.4 V, VB= 1.2 V –20 20 µA
VA= -1.4 V, VB= 1.2 V –32 0
VB= 3.8 V, VA= 1.2 V 0 32
VB= 0 V or 2.4 V, VA= 1.2 V –20 20 µA
VB= -1.4 V, VA= 1.2 V –32 0

VA= V
VA= 3.8 V, VB= 1.2 V, 0 V ≤ VCC≤ 1.5 V 0 32

VA= -1.4 V, VB= 1.2 V, 0 V ≤ VCC≤ 1.5 V –32 0
VB= 3.8 V, VA= 1.2 V, 0 V ≤ VCC≤ 1.5 V 0 32

VB= -1.4 V, VA= 1.2 V, 0 V ≤ VCC≤ 1.5 V –32 0
VA= VB, 0 V ≤ VCC≤ 1.5 V, –1.4 ≤ VA≤ 3.8 V –4 4 µA

VA= 0.4 sin (30E6 π t) + 0.5 V

VB= 0.4 sin (30E6 π t) + 0.5 V

VAB= 0.4 sin (30E6 π t)V

(1)

MAX UNIT

B,

1.4 ≤ VA≤ 3.8 V -4 4 µA

(2)

, VB=1.2 V 5 pF

(2)

, VA=1.2 V 5 pF

(2)

0.99 1.01

3 pF

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SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

t
t
t
t
t
t
t
t
t
t
t
t

(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(3) tr= tf= 0.5 ns (10% to 90%), measured over 30 k samples.
(4) Peak-to-peak jitter includes jitter due to pulse skew (t
(5) tr= tf= 0.5 ns (10% to 90%), measured over 100 k samples.

Propagation delay time, low-to-high-level output 2 2.5 3.5 ns

pLH

Propagation delay time, high-to-low-level output 2 2.5 3.5 ns

pHL

Differential output signal rise time 2 2.6 3.2 ns

r

Differential output signal fall time 2 2.6 3.2 ns

f

Pulse skew (|t

sk(p)

Part-to-part skew 0.9 ns

sk(pp)

Period jitter, rms (1 standard deviation)

jit(per)

Peak-to-peak jitter

jit(pp)

Disable time, high-level-to-high-impedance output 4 7 ns

PHZ

Disable time, low-level-to-high-impedance output 4 7 ns

PLZ

Enable time, high-impedance-to-high-level output 4 7 ns

PZH

Enable time, high-impedance-to-low-level output 4 7 ns

PZL

– t

pHL

|) 30 150 ps

pLH

(2)

(2) (4)

).

sk(p)

See Figure 5

50 MHz clock input
100 Mbps 215-1 PRBS input

See Figure 6

(1)

MAX UNIT

(3)

(5)

2 3 ps

55 150 ps

RECEIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN MAX UNIT

t
t
t
t

t

t
t

t

t
t
t
t

(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID= 200 mV

(5) Peak-to-peak jitter includes jitter due to pulse skew (t
(6) VID= 200 mV

Propagation delay time, low-to-high-level output 2 3.6 6 ns

PLH

Propagation delay time, high-to-low-level output 2 3.6 6 ns

PHL

Output signal rise time 1 2.3 ns

r

Output signal fall time CL= 15 pF, See Figure 10 1 2.3 ns

f

Pulse skew (|t

sk(p)

Part-to-part skew

sk(pp)

Period jitter, rms (1 standard deviation)

jit(per)

Peak-to-peak jitter

jit(pp)

Disable time, high-level-to-high-impedance output 6 10 ns

PHZ

Disable time, low-level-to-high-impedance output 6 10 ns

PLZ

Enable time, high-impedance-to-high-level output 10 15 ns

PZH

Enable time, high-impedance-to-low-level output 10 15 ns

PZL

samples.

samples.

– t

pHL

(LVD200A, 202A), VID= 400 mV

pp

(LVD200A, 202A), VID= 400 mV

pp

|)

pLH

(2)

(3) (5)

(3)

pp

(LVD204A, 205A), V

pp

(LVD204A, 205A), V

Type 1 100 300 ps
Type 2 300 500 ps

50 MHz clock input
Type 1 200 700 ps
Type 2 225 800 ps

100 Mbps 215–1 PRBS input

See Figure 11

= 1 V, tr= tf= 0.5 ns (10% to 90%), measured over 30 k

cm

).

sk(p)

= 1 V, tr= tf= 0.5 ns (10% to 90%), measured over 100 k

cm

(1)

TYP

(1)

1 ns

(4)

(6)

4 7 ps

6

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VAB or V

YZ

A/Y

B/Z

I

A

or I

Y

VB or V

Z

VA or V

Y

V

OS

VA + V

B

2

V

I

D

V

CC

VY + V

Z

2

or

I

B

or I

Z

I

I

VAB or V

YZ

49.9 Ω

3.32 kΩ

3.32 kΩ

_

+

-1 V ≤ V

test

≤ 3.4 V

A/Y

B/Z

D

V

OS

R1

24.9 Ω

A/Y

C3

2.5 pF

V

OS(PP)

V

OS(SS)

V

OS(SS)

≈ 1.3 V

B/Z

A/Y

≈ 0.7 V

B/Z

D

R2

24.9 Ω

C1
1 pF

C2
1 pF

V

Test

+

-

A/Y

B/Z

I

OS

0 V or V

CC

-1 V or 3.4 V

A. All resistors are 1% tolerance.

SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

PARAMETER MEASUREMENT INFORMATION

Figure 1. Driver Voltage and Current Definitions

Figure 2. Differential Output Voltage Test Circuit

A. All input pulses are supplied by a generator having the following characteristics: tror tf≤ 1 ns, pulse frequency = 1

MHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of V

is made on test equipment with a -3 dB bandwidth of at least 1 GHz.

OS(PP)

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

Figure 4. Driver Short-Circuit Test Circuit

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Output

A/Y

Output

t

pLH

t

pHL

Input

C3

0.5 pF

B/Z

D

0 V

0.9V

V

0 V

t

f

t

r

V

CC

VCC/2
0 V

SS

SS

0 V

0.1V
SS

SS

C1
1 pF

C2
1 pF

V

P(H)

V

P(L)

R1
50 Ω

A/Y

B/Z

R1

24.9 Ω

t

pZH

t

pHZ

t

pZL

t

pLZ

V

CC

VCC/2
0 V

∼ 0.6 V

0.1 V
0 V

∼ -0.6 V

0 V

-0.1 V

DE

Output With

D at V

CC

Output

0 V or V

CC

DE

Output With

D at 0 V

C1
1 pF

R2

24.9 Ω

C4

0.5 pF

C2
1 pF

D

C3

2.5 pF

SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

PARAMETER MEASUREMENT INFORMATION (continued)

A. All input pulses are supplied by a generator having the following characteristics: tror tf≤ 1 ns, frequency = 1 MHz,

duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.

Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

A. All input pulses are supplied by a generator having the following characteristics: tror tf≤ 1 ns, frequency = 1 MHz,

B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.

duty cycle = 50 ± 5%.

Figure 6. Driver Enable and Disable Time Circuit and Definitions

8

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