Texas Instruments SN65LVDT2DBVR, SN65LVDT2DBVT Datasheet
SN65LVDT2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS374B – JULY 1999 – REVISED JANUAR Y 2000
D
Meets or Exceeds ANSI TIA/EIA-644-1995
Standard
D
Integrated Line Termination Resistor
D
Designed for Signaling Rates up to
400 Mbps
D
Operates From a 2.4-V to 3.6-V Supply
D
Available in the SOT23-5 Package
D
Differential Input Voltage Threshold Less
Than 100 mV
D
Propagation Delay Times, 2.5 ns Typical
D
Power Dissipation at 200 MHz is Typically
60 mW
D
Bus-Pin ESD Protection Exceeds 15 kV
D
Open-Circuit Fail Safe
D
Outputs High Impedance With V
CC
description
The SN65L VDT2 is a single low-voltage dif ferential line receiver in a small-outline transistor
package. The inputs comply with the TIA/EIA-644
standard and provide a maximum differential input
threshold of 100 mV over an input common-mode
voltage range of 0 V to 2.5 V.
When used with a low-voltage differential
< 1.5 V
logic diagram
3
A
110 Ω
B
4
–100 mV < VID < 100 mV
H = high level, L = low level , ? = indeterminate
V
CC
GND
VID = VA – V
VID ≥ 100 mV
VID ≤ –100 mV
SN65LVDT2
DBV PACKAGE
(TOP VIEW)
1
5
R
2
3
4
A
B
5
R
Function Table
INPUTS OUTPUT
B
Open H
R
H
?
L
signaling (L VDS) driver (such as the SN65LVDS1)
in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or
cables at very high rates with very low electromagnetic emissions and power consumption.
The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the
receiving-end of the cable or transmission media. TI offers both the SN65LVDT2, which integrates the
terminating resistor for point-to-point applications, and its companion the SN65LVDS2, which requires an
external resistor. The packaging, low power , low EMI, high ESD tolerance, and wide supply voltage range make
these devices ideal for battery-powered applications.
The SN65LVDT2 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN65LVDT2
g
IC
(g)
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS374B – JULY 1999 – REVISED JANUAR Y 2000
equivalent input and output schematic diagrams
V
CC
300 kΩ300 kΩ
B InputA Input
7 V
110 Ω
7 V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
V
CC
5 Ω
R Output
7 V
†
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range (A, B, or R) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: A, B , and GND (see Note 2) CLass 3, A:15 kV, B:600 V. . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
DBV 385 mW 3.1 mW/°C 200 mW
†
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with
no air flow.
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
†
TA = 85°C
POWER RATING
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
Magnitude of differential input voltage, VID 0.1 0.6 V
Common–mode input voltage, VIC (see Figure 6)
Operating free–air temperature, T
CC
A
2.4 3.3 3.6 V
Ť
Ť
0
–40 85 °C
2.4
*
VCC–0.8
V
ID
2
V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.5
See Figure 2 and Table 1
mV
IIInput current (A or B inputs)
A
See Figure 3
SN65LVDT2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS374B – JULY 1999 – REVISED JANUAR Y 2000
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VCC = 3.6 V
2
VCC = 2.7 V
1.5
1
0.5
– Common-Mode Input Voltage – V
IC
V
0
0
VCC = 2.4 V
MIN
0.1 0.3
0.2 0.4 0.6
|VID|– Differential Input Voltage – V
Figure 1. VIC vs VID and V
0.5
CC
electrical characteristics over recommended operating conditions, VCC = 2.4 V to 3 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
ITH+
V
ITH–
V
OH
V
OL
I
CC
I
ID
I
I(OFF)
†
All typical values are at 25°C and with a 2.7-V supply.
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage IOH = –8 mA 1.9 2.4 V
Low-level output voltage IOL = 8 mA 0.25 0.4 V
Supply current
p
Differential input current (IIA – IIB)
Power-off input current (A or B inputs)
p
No load,
Steady state
VI = 0 V ±40
VI = 2.4 V or VCC – 0.8 –2.4
VIA = 0.4 V, VIB = 0 V
VIA = 2.4 V, VIB = 2 V
VCC = 0 V,
VI = 2.4 V,
Other input open
–100
3 3.6 4.4 mA
100
4 7 mA
40 µA
µ
receiver switching characteristics over recommended operating conditions, VCC = 2.4 V to 3 V
(unless otherwise noted)
t
PLH
t
PHL
t
sk(p)
t
r
t
f
†
All typical values are at 25°C and with a 2.7-V.
‡
t
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
sk(p)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Propagation delay time, low-to-high-level output 1.4 2.6 3.6 ns
Propagation delay time, high-to-low-level output
Pulse skew (|t
Output signal rise time
Output signal fall time 0.8 1.4 ns
pHL
– t
pLH
‡
|)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CL = 10 pF,
1.4 2.5 3.6 ns
0.1 0.6 ns
0.8 1.4 ns
3
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