Texas Instruments SN65LVDS96DGG, SN65LVDS96DGGR Datasheet
SN65LVDS96
LVDS SERDES RECEIVER
SLLS296F – MAY 1998 – REVISED FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
3:21 Data Channel Expansion at up to
1.3 Gigabits per Second Throughput
D
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D
3 Data Channels and Clock Low-Voltage
Differential Channels in and 21 Data and
Clock Low-Voltage TTL Channels Out
D
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D
5-V Tolerant SHTDN Input
D
Rising Clock Edge Triggered Outputs
D
Bus Pins Tolerate 4-kV HBM ESD
D
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D
Consumes <1 mW When Disabled
D
Wide Phase-Lock Input Frequency Range
20 MHz to 67 MHz
D
No External Components Required for PLL
D
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
D
Industrial Temperature Qualified
TA = –40°C to 85°C
D
Replacement for the DS90CR216
description
The SN65L VDS96 L VDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as
the SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL
synchronous data at a lower transfer rate.
When receiving, the high-speed L VDS data is received and loaded into registers at the rate of seven times the
L VDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65L VDS96 requires only four line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with data transmission
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN
)
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level
on this signal clears all internal registers to a low level.
The SN65LVDS96 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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48
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40
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36
35
34
33
32
31
30
29
28
27
26
25
D17
D18
GND
D19
D20
NC
LVDSGND
A0M
A0P
A1M
A1P
LVDSV
CC
LVDSGND
A2M
A2P
CLKINM
CLKINP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKOUT
D0
V
CC
D16
D15
D14
GND
D13
V
CC
D12
D11
D10
GND
D9
V
CC
D8
D7
D6
GND
D5
D4
D3
V
CC
D2
D1
GND
DGG PACKAGE
(TOP VIEW)
SN65LVDS96
LVDS SERDES RECEIVER
SLLS296F – MAY 1998 – REVISED FEBRUAR Y 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A0P
A0M
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A1P
A1M
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A2P
A2M
Clock In
CLK
7× Clock/PLL
Clock Out
CLKINP
CLKINM
Control Logic
SHTDN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
SN65LVDS96
LVDS SERDES RECEIVER
SLLS296F – MAY 1998 – REVISED FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
D0-1
D6 D5 D4 D3 D2 D1 D0 D6+1
D7-1
D13 D12 D11 D10 D9 D8 D7 D13+1
D14-1
D20 D19 D18 D17 D16 D15 D14 D20+1
Current Cycle Next CyclePrevious Cycle
A2
A1
A0
CLKIN
Dn Dn-1 Dn Dn+1
Figure 1. Typical ’LVDS96 Load and Shift Sequences
equivalent input and output schematic diagrams
300 kΩ300 kΩ
7 V
AnMAnP
V
CC
7 V
5 Ω
7 V
V
CC
D Output
V
CC
7 V
300 kΩ
50 Ω
SHTDN
SN65LVDS96
LVDS SERDES RECEIVER
SLLS296F – MAY 1998 – REVISED FEBRUAR Y 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any terminal (except SHTDN) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at SHTDN
terminal –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2): Bus pins (Class 3A) 4 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 3A) 3 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals unless otherwise noted.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGG 1316 mW 13.1 mW/°C 724 mW 526 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, V
IH
SHTDN 2 V
Low-level input voltage, V
IL
SHTDN 0.8 V
Magnitude of differential input voltage, |VID| 0.1 0.6 V
Common-mode input voltage, V
IC
Ť
V
ID
Ť
2
2.4
Ť
V
ID
Ť
2
V
VCC–0.8
Operating free-air temperature, T
A
–40 85 °C
timing requirements
PARAMETERS MIN NOM MAX UNIT
t
c
§
Input clock period 15.4 t
c
50 ns
§
tc is defined as the mean duration of a minimum of 32,000 clock periods.
SN65LVDS96
LVDS SERDES RECEIVER
SLLS296F – MAY 1998 – REVISED FEBRUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going differential Input voltage threshold 100 mV
V
IT–
Negative-going differential Input voltage threshold
‡
–100 mV
V
OH
High-level output voltage IOH = –4 mA 2.4 V
V
OL
Low-level output voltage IOH = 4 mA 0.4 V
Disabled, all inputs open 280 µA
Enabled, AnP at 1 V and AnM at 1.4 V ,
tc = 15.38 ns
60 82
ICCQuiescent current (average)
Enabled, CL = 8 pF,
Worst-case pattern (see Figure 4),
tc = 15.38 ns
94
mA
I
IH
High-level input current (SHTDN) VIH = V
CC
±20 µA
I
IL
Low-level input current (SHTDN) VIL = 0 V ±20 µA
I
IN
Input current (A inputs) 0 V ≤ VI ≤ 2.4 V ±20 µA
I
OZ
High-impedance output current VO = 0 V to V
CC
±10 µA
†
All typical values are VCC = 3.3 V, TA = 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
su
Data setup time, D0 through D20 to
CLKOUT↑
p
4 6
t
h
Data hold time, CLKOUT↑ to D0 through
D20
C
L
= 8 pF,
See Figure 5
4 6
ns
Receiver input skew margin§
t
= 15.38 ns (±0.2%),
TA = 0°C to 85°C 490 800 ps
t
RSKM
Receiver in ut skew margin
(see Figure 7)
c
( ),
|Input clock jitter| <50 ps
¶
TA = –40°C to 0°C 350 ps
t
d
Delay time, input clock to output clock
(see Figure 7)
tc = 15.38 ns (±0.2%) 3.7 ns
Change in output clock period from cycle
tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns,
See Figure 7
±80
p
∆t
C(O)
Change in out ut clock eriod from cycle
to cycle
#
tc = 15.38 + 0.75 sin (2π3E6t) ±0.05 ns,
See Figure 7
±300
ps
t
en
Enable time, SHTDN to phase lock See Figure 8 1 ms
t
dis
Disable time, SHTDN to Off state See FIgure 9 400 ns
t
t
Output transition time (10% to 90% tr or tf) CL = 8 pF 3 ns
t
w
Output clock pulse duration 0.43 t
c
ns
§
t
RSKM
is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clock
periods other than 15.38 ns can be calculated from
tc
14
–600 ps.
¶
|Input clock jitter| is the magnitude of the change in the input clock period.
#
∆t
C(O)
is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
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