Texas Instruments SN65LVDS95DGG, SN65LVDS95DGGR Datasheet
SN65LVDS95
LVDS SERDES TRANSMITTER
SLLS297F – MAY 1998 – REVISED FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
21:3 Data Channel Compression at up to
1.36 Gigabits per Second Throughput
D
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D
21 Data Channels Plus Clock in
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
D
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D
5-V Tolerant Data Inputs
D
’LVDS95 Has Rising Clock Edge Triggered
Inputs
D
Bus Pins Tolerate 6-kV HBM ESD
D
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D
Consumes <1 mW When Disabled
D
Wide Phase-Lock Input Frequency Range
20 MHz to 65 MHz
D
No External Components Required for PLL
D
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
D
Industrial Temperature Qualified
T
A
= –40°C to 85°C
D
Replacement for the National DS90CR215
description
The SN65L VDS95 L VDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out
shift registers, a 7× clock synthesizer, and four low-voltage dif ferential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted
over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65L VDS95 on the rising
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS95 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The
only user intervention is the possible use of the shutdown/clear (SHTDN
) active-low input to inhibit the clock
and shut off the L VDS output drivers for lower power consumption. A low level on this signal clears all internal
registers to a low level.
The SN65LVDS95 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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26
25
D4
V
CC
D5
D6
GND
D7
D8
V
CC
D9
D10
GND
D11
D12
V
CC
D13
D14
GND
D15
D16
D17
V
CC
D18
D19
GND
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV
CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)
SN65LVDS95
LVDS SERDES TRANSMITTER
SLLS297F – MAY 1998 – REVISED FEBRUAR Y 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D0–6
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D7–13
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D14–20
CLKINH
7×CLK
7× Clock/PLL
CLKIN
Control Logic
SHTDN
CLK
A,B, ...G
A,B, ...G
A,B, ...G
7
7
7
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
SN65LVDS95
LVDS SERDES TRANSMITTER
SLLS297F – MAY 1998 – REVISED FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
D0-1
D6 D5 D4 D3 D2 D1 D0 D6+1
D7-1
D13 D12 D11 D10 D9 D8 D7 D13+1
D14-1
D20 D19 D18 D17 D16 D15 D14 D20+1
Current Cycle NextPrevious Cycle
Y2
Y1
Y0
CLKIN
’LVDS95
Dn
Figure 1. ’LVDS95 Load and Shift Sequences
equivalent input and output schematic diagrams
V
CC
7 V
300 kΩ
50 Ω
D or
SHTDN
50 Ω
V
CC
YnP or
YnM
7 V
10 kΩ
SN65LVDS95
LVDS SERDES TRANSMITTER
SLLS297F – MAY 1998 – REVISED FEBRUAR Y 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any output terminal, VO –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any input terminal, V
I
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2): Bus pins (Class 3A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus pins (Class 2B) 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 3A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGG 1316 mW 13.1 mW/°C 724 mW 526 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Differential load impedance, Z
L
90 132 Ω
Operating free-air temperature, T
A
–40 85 °C
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